Beseitigung von EMI-Problemen in der Designphase, robustes EMI-Interference-Testing und Ebenenresonanzanalyse

Yoshi Fukawa
|  Erstellt: February 3, 2022  |  Aktualisiert am: July 13, 2022

Dank der Zusammenarbeit mit NEC Solution Innovators sind in der Altium-Designer-Umgebung nun auch die sehr wichtige EMI-Design-Regelprüfung und die Ebenenresonanzanalyse verfügbar. In diesem Vortrag zeige ich Ihnen, wie schlechte EMI-Designs zu ernsthaften EMI-Problemen führen und wie man EMI mit Hilfe von EMI-Design-Regelprüfungen, EMI-Interference-Testing Ebenenresonanzanalysen bekämpfen kann. Einige der wichtigsten Regeln für effektives EMI-Testing erläutern wir anhand von Simulations- und Versuchsergebnissen.

Zusätzliche Ressourcen zum Thema EMI-Prüfung:

Transkript:

Yoshi Maruyama:
Hi everyone, I'm Yoshi Maruyama from NEC Solution Innovators. I'm a director of R&D responsible for EMS team development. 

Yoshi Fukawa:
Hi, I'm Yoshi Fukawa from TechDream, US distributor of EMIStream based in Silicon Valley California. We are team W Yoshi. Today team W Yoshi will talk about eliminate EMI problems at the design stage robust to EMI design wall tech and the plane resonance analysis at your desktop. So let's get started with technical presentation first from Yossi Maruyama from NEC. Yoshi, take it away.

Yoshi Maruyama:
Thank you for joining this session, very important EMI design rule check and plane resonance analysis are available in the Altium Designer environment. This talk will show you how bad EMI design cause serious EMI programs and how to mitigate EMI using EMI Design rule check and plane resonance analysis. We will explain some of the most important rules with simulation and experiment results. Before this presentation, let me introduce myself. I'm Yoshiaki Maruyama from NEC Solution Innovators. I have been developing EDA software for 19 years, and I studied EMC technology to make our software better. 12 years ago, I was certified as an EMC design engineer by KEC & iNARTE. Now I keep running to serve as an EMC committee member for JIEP.

JIEP is a Japanese Institute of Electronics Packaging, one of the largest academic society in electric packaging in Japan. I submitted several joint papers to JIEP. Today's presentation includes some examples from the paper submitted to Jiep in 2007. As you know, NEC is a giant company in Japan and develops a lot of product as below. However, we were facing a lot real world EMI problems with this products. EMC engineers sometimes had three plus press night at the chamber for researching EMI factors and fixing the problem. So we started investigating EMI root causes with EMC teams from different division in NEC. 

After investigating over 150 EMI root causes we did reach most important EMI root causes. There are mainly two EMI root causes, one is related to EMI design rule on PCB. And another one is related to power plane resonance in between power and ground plane. Please take a look at the below chart. As for EMI design rule, we classified with three categories. First one is related to signal traces, the second one is related to return path discontinuity, and the third one is related to power and ground plane. Today I will explain most important EMI design rules, return current path discontinuity, traces near plane edge, and decoupling capacitor and show you the basic knowledge on how to solve EMI issue.

I will also explain about power plane resonance, why plane resonance occur and how to mitigate the plane resonance to reduce EMI. Firstly, I'll disclose the basic knowledge of return current path. The ground plane near the signal trace must be continuous. The nearby ground plane is a path of the return current. If the return current path is discontinued, EMI noise may occur. This is an example of single ended signal. There's a signal lying on the top layer, it's covered with the whole ground plane or the second layer. 

If current which frequency is less than one megahertz rolls into trace, like this arrow return current flows into the shortest path in ground plane like this dashed arrow. In the case of frequency is more than one megahertz return current flows into ground plane along with signal trace like its shadow. This is a case that traces across the street on the plane. If a high speed signal trace crosses over a slit, return current detours around the edge of the slit.

This detour is called return current path discontinuity. It makes EMI noise closure. In this slide, I explained the behavior of near field in the case of return current path discontinuity. This test both board is two layers, the top layer has AC and signal trace. The bottom layer has ground plane, and there are slits on the ground plane here. High speed signal is crossing over the slit. This shows the near field behavior on both sides. We can see the return current flows along with the trace and the edge of slit. The magnetic field is expanding from it's slit, this will be a critical noise source.

Basically, the magnetic field occurs only between signal trace on the first layer, ground plane on the second layer, but in this case the magnetic field is diffused from the slit to the back side. This was a very interesting measurement result. Spread of this magnetic field shows a strong electric field intensity in the far-field as common mode noise. This is a result of far-field. 

The measurement results when the slit on the ground is gradually expanded is plotted. The black line is the radiation level in the case of no slit, that's an ideal condition. As you can see the longer slit wheels, the stronger electric field strength can be observed in far-field. 

The red line is radiation level when the slit is 10 millimeters, that is the return current turns five millimeters. The result of no slit, black line and 10 millimeters red line. Their almost same in the far-field. So the return current path discontinuity check of EMIStrem are over the detour within five millimeters by default. 

This is a case of a six layer PCB. On the left side, signal trace runs on the first layer. It goes through up here. There are ground plane on second layer and the power plane on fifth layer. The return current path flows mainly the near from a signal trace. So, the return path of top layer flows into the second layer and return path of the fourth layer flows into the fifth layer. 

As a result, return current path doesn't continue between second layer and fifth layer. The right side is the case that signal trace lands on the top and third layer. In this case, the return current runs on the second layer because the near spread of signal trace is the ground plane therefore, return current path continues. To compare with the far-field, we can find the right side is better than the left one.

How about adding a capacitor near the second layer? By adding a capacitor the return current continuously flow through a capacitor. As a result, the radiation level becomes smaller than the left case. It is important to keep the shortest return paths as possible by improving layer plan or adding a capacitor. That is the explanation of return current path discontinuity. EMIStream automatically can detect this layered pattern. For the next either describes the basic knowledge of traces near plane edge. High speed shell must not pass through the edge of the ground plane. The return current of signal flows through the edge of the plane exiting the entire plane.

As basic knowledge, I will explain the return current distribution of signal trace. This figure shows the case where the signal trace keeps enough distance from the ground plane edge. In general, the return current of signal trace flows from the air three times the width of signal trace on the ground plane directly below the signal trace like this figure. In this illustration, the distribution of return current from the center of the signal trace is symmetrical, because the signal trace has enough distance from the edge of the ground plane.

On the other hand, if the signal trace is close to the edge of the ground plane, some of return current flowing through the ground plane will be missing as shown in the red section of this figure below. As a result, straight current occurs at the right end of the ground plane exiting the plane because the ground plan itself has a dipole antenna structure, this electric current energy causes radiation. This is a result of simulating the distance between signal trace and ground plane edge and electrical field intensity in the far-field.

The far left of the horizontal axis is 0.1 millimeter, which is when the signal trace is almost at the edge of the plane. From these results, it can be read that the radiation nodes decreases the signal trace is away from the edge of the plane. After confirming the quantitative reduction effect by simulation we initially decided the design rule of two millimeters from the plane edge as a realistic value. In other words, the design rule is that signal trace should exist further down two millimeters from the age of the plane.. pattern that violate this rule. The last rule is decoupling capacitor. The capacitor must be placed near the IC power pin. The closer the capacitor is to the power pin the more effective it is. 

First, I will explain the noise going from the IC to the power and ground. There are two types of high frequency currents which flows into the power and ground of IC. The first type is a charge/discharge current, the current flowing through the signal trace. This is example of equivalent current for driver IC in a CMOS structure.  When the signal becomes from low to high level, current flows from the driver IC power pin to the signal trace. When the signal becomes from high to low level, current flows from the signal trace to the ground pin of the driver IC. When the signal operates, it flows between the power earth and the noise source in this way.

The second type is feed-through current from growing from the power to the ground. Variation in the input voltage causes signal to go from low to high level or from high to low level. The intermediate potential of input voltage, there is a time when both P channel and L channel are turned on intaneously at which time high current flows from the power to the ground.

These two types of the noise current to flow between the IC power and ground pin. A capacitor is placed to suppress noise source between power and ground which is called decoupling capacitor. Charge/discharge current and feed through current from IC and by adding capacitors, you can separate the noise from the main power and prevent noise from flowing out to the main power plane. Decoupling capacitor can supply the electric charge required for charge/discharge current and PD through current preventing noise diffusion near the IC. And we see it is our internal rule to place capacitors within five millimeters of the IC pin. So far I have explained the impact of the far-field caused by the return current path discontinuity and traces near plane edge. 

The basic knowledge of decoupling capacitor. High speed signals require a continuous return current path, however, return current meters is acceptable and it is also effective to the capacitor to keep the return path. In addition, it is recommended that high speed signal be routed at least two millimeters inside plane edge. Decoupling capacitors must be placed near a power pin. Manually checking the design rule can be time consuming and costly, therefore automation with design rule checker such as EMSStream is essential and effective is the actual design work flow. Next, I will explain the basic knowledge and verification results of plane resonance between power and ground plane.

Generally, there are various antenna patterns in PCB. Single ended signal behaves like a loop antenna. PCB and its cable behaves like a dipole or monopole antenna. A slit on the plane behaves like a slot antenna. Power and ground plane facing each other behaves like a patch antenna. Plane resonance between power and ground will be one of the dominant factors for EMR. When the resonance frequency of antenna accord with noise source, the initial noise is strongly emitted. We can think simply, noise source multiplied by antenna factor equals length of far fied in each frequency. 

Regarding the noise source IC and high speed signal traces are the dominant noise factors. But there is a limitation to separate the noise source factor. Regarding the antenna factor, a pair of power on the ground plane is one of the large antenna in PCB and it's factor is controllable. Therefore, it is important to calculate the resonance frequency in advance and reduce radiation effects efficiency of the patch antenna at layer design stage. The resonance frequency of plan can be obtained with such a simple formula.

In this formula, the plan has AB metal horizontal ranks, and vertical ranks is BB metal, and M and N are the natural number of.. For example, suppose that A is 300 millimeters, and B is to 200 millimeters and the MN mode is calculated. In one zero mode resonance frequency is 220 megahertz. It is anti-node, node, anti-node in the horizontal direction of the board.

In 01 mode, the resonance frequency is 345 megahertz, anti-node, node, anti-node in a vertical direction of the board. From these color gradation, you can see that wavelengths in 01 mode is shorter than that in one zero mode. When the resonance frequency increases in this way, it resonates with a complex voltage distribution. It is possible to calculate resonance of such a simple rectangular plan but in actual PCB design, the plan has more complex shapes.

Another calculation method is SPICE analysis by using PEEC method. In this case, cutting the voltage plane and ground plane into mesh panel and converting to LCR model in each mesh. For capacitors on the plane, they're converting to ACR model including ESL/ESR will bring out traces and then they connect to the nearest mesh node. After that it applies one bolt 50 noise source. By using SPICE analysis, it calculated maximum voltage in each node for each frequency by displaying the result of each node on the layer screen. It is possible to visually check the anti-node or the node of resonance.

This graph plots the maximum voltage value for each frequency based on SPICE simulation results. In the graph where the horizontal axis is the frequency and the vertical axis is the voltage level. The frequency with the PEEC becomes the resonance frequency. In the plane resonance analysis, it is possible to show the high sinking voltage area in each resonance frequency on the layout display. As a countermeasure against resonance, place the capacitors are the hot spot, this reduces voltage variation between power and ground plane by checking the gradation of the voltage distribution for each resonance frequency and adding a capacitor at a position of resonance anti-node.

Resonance countermeasure can be easily implemented for anyone. In actual PCB design, if such assimilation is not performed, capacitors may be placed at the rate of several tens of millimeters intervals on the design rule basis because placing too many capacitors increases manufacturing cost. It is good idea to use simulation to consider the minimum number of capacitors required.

Finally, I'd like to introduce the use case of plane resonance analysis. This is a four year wall with a length of 19 millimeter and width of 154 millimeters. The second layer is a ground and the third layer is a board. It is a simple board with a socket in the upper left of the board and exited the power on the ground at 33.3 megahertz. The other part in the far corner of the board where capacitors on RC snubber circuit can be placed.

RC snubber use a small resistant in slit with a small capacitor. This is a case of changing the resistance value of the snubber circuit to verify the optimal resistance value. This is a result of comparing resonance analysis by EMiSStream with near field measurement. As a condition, the path in the four corners does not have a capacitor. Firstly we confirmed that resonance frequency and voltage distribution matched in simulation and actual measurement.

This is a result of far-field measurement, we measured five cases. The first is a case where nothing is mounted in the four corners of the board. It is the same condition as the previous near field measurement. In the second case 0.1 megahertz is placed in the four corners of the board. In the third case snubber circuits are placed in the four corners of the board. The snubber circuit, it's a serious circuit of 0.1 megahertz and one. In the fourth case, the distance value over the snubber circuit in the whole corner is 5.1 volts.

In the fifth case, the distance value of a circuit in the four corners is 22 volts. Since it is difficult to understand when the five measurement results are displayed as they are, we changed it to the line graph with 33 megahertz multi graph. In conclusion, there was no common resistance value that lead to good results at all frequencies. For example, at 166 megahertz, the lower the resistance the less radiation noise. On the other hand out 900 megahertz, the lower the resistance, the higher radiation. In this case, it is required to determine the resistance value according to the specific frequency to suppress.

This is a result of SPICE analysis by using PEEC method. In this graph, where the horizontal axis is frequency and the vertical axis is impedance between power and the ground. The frequency of the PEEC becomes the resonance frequency. The result where there is no snubber in the fourth corner in the red line of this graph. By placing the capacitor of 0.1 micro, the resonance frequency is shifted to the high level. By adding a resistance of 1 ohm the quality factor is lowered. This is because high frequency noise current changes to the thermal energy due to resistance.

In addition, if the resistance value increases to 5.1 ohms, the resonance PEEC decreases. When the resistance value is set to 22 ohms, the impedance of snubber circuit increases, so it approaches state where there are no snubber circuit. By using the SPICE simulation, it is possible to easy trial and error the constant of the snubber circuit. This is a result of comparing the frequency graph of the resonance analysis or with the actual measurement of the far-field. As you can see, if the dominant factor of radiation is the plane resonance, it can be correlated with the actual measurement of the far-field. In the actual design, it is necessary to perform simulation in advance to control the resonance between power and ground at the layer design stage.

Today, I explained the important design rules return current path discontinuity, traces near plane edge, and decoupling capacitor 15 EMI rules. The basic knowledge and verification result of power plane resonance analysis. Now, EMI design rule check, and ultra resonance analysis are available in Altium Designer extension. From now on Yoshi Fukawa will start the demonstration of EMIStream extension. Yoshi, take it away.

Yoshi Fukawa:
Thanks Yoshi. And it's Yoshi again from TechDream. As Yossi explained, this EMI design rule and plane resonance analysis is very important to mitigate EMI. So NEC developed and commercialized EMIStream back in 2002, more than 20 years ago, but now EMIStream is available in Altium Designer. So if you open Altium Designer you'll find these extensions and upgrades, you can find these EMIStream extensions with EMI design rule check and plane resonance analysis. After downloading these EMIStream extensions, you will find the EMIStream in tools menu with EMI design rule check and plane resonance analysis. 

Let's take a look at how to solve EMI problems with this EMI design rule check and the plane resonance analysis. I will show you EMI design rule check first. If we go to tools, EMI design rule check automatically converting into ODB++ file and the opening EMIStream. So this is EMIStream opening screen. If we go to edit and backup, this backup was automatically imported from Altium Designer with thickness each layers and the DK and the DFL tangent. So you don't need to set anything, it will automatically import it from Altium Designer.

And then there are two another net property, in other words component property. So if we select net property, this is the net list from Altium Designer, so we have to set the frequency for all the high speed real quick just for example, I'm going to set the 150 megahertz for this high speed RU, I can just copy and paste for our units. And then we also have to set the voltage this purple line 1.2 volt lane and 1.8 volt lane as seen on it.

[foreign language 00:38:28] And then if you have any signal data trace or differential pair trace, we can set it here and just to set properly, we have very full feature associating rules with different resonance designator. So, if we have a resonance designator like a C something, U something, something, EMRStream automatically recognize this components and then set as a connector, capacitor, resister same as net. For example, if your net name has a GND or VCC for power EMIStream automatically recognize and sends it to ground or power plane, the same as differential pair.

If your net name PN or plus minus four it must be automatically recognized and set to the differential pair. So setup is very, very simple and very fast. Now it's ready to check. And then we have parameter GUI for each setting. So, this is a 50 EMI design rule check including trace lengths check and via count, tracing the plane gets checked as Yoshi explained before and this is a reference change check and return current path discontinuity. Estimated ratio has actually this equivalent circuit model and predict on the EMI from a loop area. 

And there are auto trace via spacing check grounding via long plane check, or filter check and decoupling capacitor check is also important, as Yoshi explained area. And the differential pair check length difference, parallel check, impedance and balance check ensemble check and phase check. And we also have crosstalk check and digital interference check, overlap check, and IC ground split check. You can rely on these threshold parameters for pass/fail analyses. 

But if you have any internal design guideline, you can of course customize these shield numbers. But if you don't have, you can rely on these default parameters. These parameters were already investigated by NEC using simulation or experiments. So now is ready for simulation, you can just click the EMI rule check. So now checking all 15 rules at once. This is a check result with color gradation. Actually, red color has higher risk for EMI. So red, orange, green, yellow or blue. Actually we have error point as higher risk for EMI.

For example, this net, the out 25 error points including gradient error or reference change era or return current path discontinuity errors. If we double click this error, this leads you to the era location now here. So this the error. And then if we double quick refine change, it leads you to the error location, but not only error location, but also error explanation why this is error. But not only error explanation, but also giving the solution how to fix this problem. So actually you can pass these solutions to the PCB layout engineer to fix this problem.

Same as return and current path discontinuity, this is a split plane on return path discontinuity over the plane replaying over the split plane. And then this is era after the filter features. So you can turn them all and you can just see, for example I already explained that plane edge return current path discontinuity. So again, just select estimated radiation and then double click. This is actually estimated EMI from this loop area using this equation. You can see either differential model, classical model or only differential model on the board.

And then another way is.. Playing out to lie and check. So this is a ground plane check. If we double click, EMIStream recommends to put the ground stitching with a red circle locations here, here, here, here, here, because if we don't have the [vias 00:44:40] this portion becomes antenna to radiate EMI. So, EMIStream recommends to put the grounding with via PTs. And then this is a decoupling capacitors, as Yushi explained earlier. It's very important. So, if we double click here, this is IC and this is the decoupling capacitor is far from power pin. EMIStream recommends to actually change this location.

And also a very unique feature is we can visualize the return current path because minimizing return current path or the decoupling capacitor is very important. Actually we can visualize the return path so it's very easy for us to identify whether the capacitor location is good or bad. This is the decoupling capacitor check and this is a differential pair check. Differential pair check is also important. If we double click, the balance match is very important. This is a plus minus and this inside trace and outer trace lengths is different so due to skew it causes EMI so EMIStream checking this on differential pair check.

We may have a lot of errors, but we want to prioritize the errors. So we have a filter features based on the importance of each rules and their frequencies so we can just edit the weight for each errors. For example, if you think reference change is very important, above 100 megahertz, you can set these as high priority or specify mid priority or low priority to focus on all the critical errors. This is the filter feature, and also we have a report generation features we can create these report in Excel format. That's all about EMI design rule check. 

Now let's move on to the plane resonance analysis. If we select tools, plane resonance analysis, again combining into the ODB++ file and now opening EMIStream with plane resonance analysis menu, same thing already imported and net property already imported and a component property we are using this capacitor model for each capacitor. But automatically we must import the capacitance model based on the path name or capacitance value. 

So You don't need any anything to set for this capacitor model for resonance analysis. And then this is in the power plane on the third layer and the second layer is the ground. When resonance analysis flow between power and ground plane we have to specify the power plane first. So if we go to plane resonance analysis, first we have to specify the power plane. This is a power 3.3 volt plane and also we have to specify the reference ground plane. So this is the second layer ground. And then these parameters like dielectric thickness, or copper thickness DK DF, automatically imported from Altium Designer so you don't need to set anything, but you can also manually change these thickness.

So you can play with a different thickness or different DK or different DF. And then if we go to option this is a mesh size, we have to set the mesh size. Final mesh size can have accurate result but takes longer. And then we have to specify the component capacitor library and the minimum clock frequency and maximum clock frequency. We may want to see the fundamental clock frequency and we see actually harmonics up to one gig. And then just okay, and then just to run simulation, as you can see, it's very fast with the PEEC method and fast SPICE engine. 

This red portion has higher resonance, and if we take a look at VF graph spectrum chart, we have resonance around 870 megahertz. The chart is no good and we have to reduce the resonance. NEC recommends below -10 dB. This accelerates highlighted components as a decoupling capacitor. So we can just copy these capacitors or we have very cool features to raise capacitors automatically. If we go to auto place, we can select capacitor model either auto or fixed.

If we select auto it must be automatically select optimum decoupling capacitor and the place onto the optimum location to reduce resonance below -10 dB and reputation 10 times and run. So now EMIStream is selecting optimum decoupling capacitors, usually lowest impedance capacitors to the highest PEEC. Actually, EMIStream, added three capacitors, so if we double click this capacitor to the MSD model capacitor in here and then if we take a look at the spectrum chart again, this is the original result after adding one capacitor, two capacitors, three capacitors, actually below minus -10 dB to reduce resonance, and that is okay.

You must automatically select and decoupling capacitors and place on the optimum location to reduce resonance. And then if we click component list, this is actually the decoupling capacitor list for this particular power plane. We also have far-field EMI prediction estimation from PDM plane structure because, power plane becomes patch antenna to radiate EMI from the edge of the PCB. 

So if we place the PCB onto the turntable, we can specify PCB position and the PCB orientation like horizontal or vertical one, and then we can specify distance to antenna the either three meters or 10 meters or 30 meters. Antenna height is usually from one meter to four meters. I can just set one meter, and the turntable's tape, we can set and then okay. This is actually a far-field EMI form PDN structure. We can see this vertical and horizontal EMI and also, we can see the radiation pattern which direction we can have EMI most.

So, we can compare with EMC chamber measurement results. If these PEECs are matching to the MSE chamber measurement, these PEECs most probably are coming from the resonance between power and ground plane. So we have to reduce that resonance to mitigate EMI. That's for the power plane resonance analysis.

That concludes our presentation and demo. If you have any further questions, please visit our virtual booth at AltiumLive. We also have one month free trial lessons. So if we want to evaluate, please let us know. Thanks for watching and have a great day. Bye bye

Über den Autor / über die Autorin

Über den Autor / über die Autorin

Yoshi Fukawa received his B.S. degrees in Electrical Engineering from Tokyo University of Science, Japan, in 1988. He received a certification of NARTE EMC Engineer in 2000. He used to be an EMC committee member of JEIDA in Japan and currently a member of IEEE EMC Society. He is a founder of TechDream based in Silicon Valley who has been providing leading-edge EMC solutions carrying EMI simulation software, near-field EMI scanner and advanced PCB materials in US. He submitted several joint-papers to IEEE EMC Symposium, DesignCon and EMC Europe.

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