Best Methods For Design That Satisfies Power Integrity Parameters
In my previous articles, I addressed Power Delivery System (PDS) design, the myths surrounding it and ways to implement a successful working PDS. At the core of all these efforts lies power integrity. What is it? What are the challenges associated with it? How can it be successfully incorporated into a fully-functioning PCB implementation?
This article will address the beginnings of power integrity, the various facets of component functionality that affect it, and the best methodologies for ensuring that your design satisfies power integrity parameters. Part 1 of this blog defines the problem while Part 2 will describe how to solve it.
The Genesis of Power Integrity
When it comes to today’s electronic products, we are once again faced with the good news/bad news scenario. The good news is that we have lots of functionality in ever-shrinking geometries. The bad news is that this combination creates more complex PDS problems. The evolution process is as follows: The technology continues to decrease in feature size, resulting in a decrease in power per logic gate; an increase in gate count per chip; an increase in clock frequency and a lower power supply voltage. With these lower power supply voltages, higher power per chip and higher clock frequencies the PDS becomes increasingly difficult to design relative to successfully maintaining power integrity.
Stated simply, power integrity means designing a power source that is capable of delivering a charge or energy so that the digital circuits can do their job. In the “dark ages” when we first started designing things with logic, the world did not need speed. Power could be hooked up pretty much in any manner and things would work. The mantra became “it’s only logic.” This kind of thinking actually held true if products were being designed with TTL because it was painfully slow.
On the other side of the world, there was ECL and it was the only logic that was capable of doing high-speed computing. This was the world populated by IBM, Cray and Amdahl. ECL engineers “got it” in terms of PDS design because ECL required a high level of PDS engineering. But, ECL occupied a rarified, small fraction of overall product designs so power integrity as a design discipline was very limited.
Because TTL was the primary logic technology being used and power delivery was not an integral part of it, it became the incubator for the “rules of thumb” that came into being with no solid engineering serving as the basis.
The Elements That Comprise a PDS
An “ideal power subsystem,” as depicted in Figure 1 would be a fixed voltage source with zero output impedance at all frequencies. And, this ideal power subsystem would deliver a constant voltage to the load independent of load current changes. The problem is that with today’s electronic products there is no such thing as an “ideal power subsystem.”
Figure 1. Ideal Power System or Voltage Source
Lee Ritchey, President and Founder of Speeding Edge notes, “People make the assumption that a PDS is a voltage source without any proof that it is true. The definition of a voltage source is that no matter how much current you draw, the voltage stays the same. That’s the first bad assumption. The second bad assumption is that this remains true at every frequency. And, that’s where it all comes unraveled and it’s the reason products fail.”
There are two main problems in designing a functional PDS. The first problem is making the impedance low at high frequencies. The second problem is making sure there is enough copper in the PDS to minimize voltage drops. Then, when the insanely high currents that are in use today are added, the problem becomes magnified several times over.
What Type of Information Is Needed?
The challenge is that it is difficult to get really good information as to what the ICs require in terms of loads. Ritchey says, “We still don’t get good data from hardly anyone. If the data says the peak current is ‘X’ amps, we have to design the PDS as if the Delta I, or changing current, is from zero to whatever that peak is. And, you have to assume the position of being a pessimist. You go with the worst case scenario and then, based on that information, engineer the PDS from there.”
In truth, the IC companies are getting better in terms of the amount and quality of information that they provide. It used to be that logic design was comprised of four kinds of components: microprocessors, FPGAs, network processors and memory. FPGAs and processors have basically taken the place of all of those elements that used to be separate entities. Because a large part of most logic designs is done in FPGAs the component vendors can’t tell what the power requirements are going to be. They don’t have insight into the interior of the part in terms of how it is going to be used so it’s difficult for them to quantify how the power integrity of the part can be maintained.
Further, the technology has evolved such there is no discreet logic anymore. Ritchey explains, “It’s just gigantic building blocks that are comprised of billions of transistors in the cores of the ICs. And, the high currents that are switching are resident within these cores.”
With all of the huge functions that are integrated into any one IC, all of the interconnections that used to exist between three or four ICs have vanished. Now, there are multiple power supplies on one PCB because of all the functions that take place in any given IC. This is referred to as “point of load PDS Design.” Ritchey states, “Now, you put the regulator right next to the IC. In most cases, there will be at least two or maybe three power supplies for one IC. When you multiply the number of power supplies required for the number of ICs on one board, the complexity of the PDS design process increases accordingly.”
How Do You Know if Your PDS Will Work Properly?
Part of the power integrity problem arises from the fact that we became complacent when it came to hardware design. For years, the value-add has originated from software. Our view has been that hardware is a “no surprises” design element so when it came time to be concerned about power integrity, we were caught with our proverbial guard down. Power integrity problems were essentially unknown and not readily understood. By the time we realized that there were new parameters that needed to be addressed, we were many days late and several dollars short in terms of incorporating power integrity into current and next-generation designs.
As noted above, getting good data on IC power loads has been and still is a challenge. To offset this, there are a number of good EDA tools in existence that can simulate an entire power delivery system. The load information provided by the IC vendor can be simulated and, from there, it can be determined if the design is headed in the right direction. The biggest challenge is the cost of the tools and the skills needed to use them.
Ritchey states, “One of the biggest challenges that I have encountered is getting management to understand why these tools are necessary. It’s one of those ‘I never needed it before, why do I need it now’ mentality?’ It’s a big investment for a tool that is not required all the time. There’s also the challenge of engineering skill sets. About half the time engineers don’t know that they need to do this kind of simulation exercise. They’ve not had to do it before and it’s a lot of work to get up to speed on the toolset technology. In reality, until they encounter a problem in PDS design, engineers don’t start to do their homework.”
So, is PDS simulation all that is needed? “I had to start doing complex PDS design in 1999,” Ritchey notes. “Most of us tapped into what Sun Microsystems was doing because they had about the best power delivery engineering going at the time. They did lots of test boards and they were kind enough to report the results with the IEEE.”
“Starting way back at Amdahl, I built my own test boards because we knew that was the only way we were going to get the information we needed,” Ritchey says. “And, it’s the only way that you are going to know for certain if your PDS is going to work. Over the years I have built just about every kind of test board needed. When you design some two or three thousand boards, you have a sense of what you have to do when things get complicated.”
Between the foregoing elements—better and more complete information from IC vendors, PDS simulation tools and test board information that is shared across the industry, there is a good foundation for designing your power supply system. The challenge is staying on top of the evolution of the technology. Ritchey explains, “Power supply issues get more complex because the currents go up.
And, there are more transistors that are made increasingly smaller. Because they are smaller, the operating voltage has trended down. Now, we are faced with how to deliver 160 amps to an IC at only .9 volts at a wide range of frequencies.”
Ensuring that power integrity is adequately addressed in any given design implementation is still a learning issue. IC vendors are better about providing power load information for their parts but the wide-spread use of FPGAs means that the component vendors don’t have enough insight into how their part is going to be used to guarantee power integrity. And, even though simulation tools have significantly improved, there still is no substitute for building a test board that will ensure your product will work as designed.
Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium or continue reading for guidance on how to successfully engineer the Power Delivery System (PDS) so it meets the needs of new technologies with Altium Designer®.
Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.”