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    Comparator Propagation Delay in High Speed Mixed-Signal Design

    Altium Designer
    |  August 20, 2018

    IC on blue PCB with high-density trace routing

    When I began my journey into the wonderful depths of electronics so long ago as a student, I wondered how so many interesting and important functions are built into everyday electronic devices. Input signal and voltages were fresh in my head and I was worrying more about a power supply than inverting inputs. It wasn’t until later that I started to fully understand the versatility of op-amps and how they could be used to build comparators.

    Comparators are important components in PCB design that don’t receive the attention they deserve. Although they come packaged in ICs, a variety of comparators can be built from amplifiers as well. The propagation delay in these circuits is important in high-speed design, and it is important to understand how different PCB design issues affect comparator propagation delay.

    Comparators vs. Op-amps

    The basic idea behind a comparator is to determine whether an input offset voltage is higher or lower than a reference voltage. When the reference voltage is kept at a constant DC level, a comparator can function as a kind of analog-to-digital converter. The comparator outputs HIGH when the input analog signal rises above the threshold voltage.

    Comparators are actually related to op-amps. Simple comparators can be built from an op-amp operating with an open loop configuration. The open loop pushes the overall gain of the amplifier to infinity. This quickly saturates the output in the ‘HIGH’ state, thus allowing an AC signal to be converted to a square wave. Nonlinear saturation also helps suppress voltage fluctuations at the comparator input.

    Just like any transistor-based logic device, there is some propagation delay associated with the rise time of the output signal (not to be confused with transmission delay). Unless a comparator is manufactured to exacting specifications, your manufacturer will not provide tight specifications on the value of propagation delay. Popular comparator ICs will provide a mean output value and a variation range that can be as large as 30% from the mean value.

     SMD components on a PCB

    SMD components on a PCB

    Despite the natural voltage fluctuation suppression, the propagation delay range for most comparators is massive compared to other standardized parameters for ICs. The long rise times in op-amp comparators place an upper limit on the frequency of the analog signal on the input to approximately the low-MHz range. However, newer comparators that are not based on infinite-gain amplification can work properly with frequencies over 100 MHz.

    These newer comparators do not have the internal Miller capacitance found in op-amps, and this ensures rise times are extremely quick due to a lower equivalent RC time constant at the comparator input. This absence of inherent compensation causes comparators to have wide input bandwidth. This also translates into reduced propagation delay, making these comparators preferable over amplifier-based comparators in higher speed and higher frequency circuits.

    PCB Design Factors Affecting Comparator Propagation Delay

    The primary factor that affects the propagation delay of a comparator is the output capacitance and stray capacitance. The resistive load at the output also affects the switching speed of a comparator. Optimizing these parameters allows a to select the best tradeoff between propagation delay and noise immunity.

    Parasitic capacitance already creates signal problems in high-speed PCBs, but it creates even more issues in comparators. The output load from a comparator already tends to be inconsistent from manufacturer to manufacturer. Any parasitic capacitance that affects the comparator output will change the rise and fall time, thus changing the propagation delay. In general, the propagation delay is linearly related to the output capacitance; an increased capacitance increases the propagation delay.

    Measures should, therefore, be taken to reduce stray capacitance near comparators used in high-speed PCBs. Some options include reducing pad sizes at the pins of a comparator, using a series capacitor to compensate for abnormally high capacitance, and obeying important trace spacing rules.

    Black capacitors on PCB

    Black capacitors on PCB

    The output of a comparator can be easily modified using a pull-up resistor connected to the positive supply voltage. This feature allows designers to interface the comparator with a variety of logic families. The propagation delay can be improved by using a smaller pull-up resistor. A smaller pull-up resistor also improves noise immunity, but it also increases current and power consumption.

    Decreasing Noise Sensitivity

    All comparators have a quality called hysteresis. If you look at a graph of the output voltage versus the input voltage, the curve traced by the data points do not follow the same curve. As input voltage increases from zero, the output voltage saturates. As the input voltage is now decreased from the saturation point, the output voltage de-saturates at a different rate. This up-and-down cycling of the input voltage creates a hysteresis loop.

    While hysteresis is typically viewed as undesirable in electronic components, it is actually useful for noise suppression in comparator circuits. Positive feedback is often used in amplifier-based comparators to provide the high gain required to drive them into saturation. The positive feedback loop increases the size of the hysteresis loop, leading to better noise suppression.

    So how can you start using comparators in your high-speed or high-frequency circuits? The advanced routing and simulation tools in Altium Designer® can help you avoid signal integrity problems. Now you can download a free trial and find out if Altium Designer is right for you. Talk to an Altium expert today to learn more.

    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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