DC Analysis of a PDN: Essential for the Digital Designer

Jeff Loyer
|  Created: February 21, 2017  |  Updated: September 25, 2020
As PCBs become increasingly miniaturized, engineers are commonly faced with incorporating multiple power planes on the same layer. While this design practice introduces coupling issues, the real question is whether they can be resolved without a dedicated PDN analysis tool. Read on to find out.

DC Analysis of a PDN: Essential for the Digital Designer

Is there enough copper?

DC analysis of a power delivery network (“PDN”), commonly referred to as “IR drop”, “DC power integrity”, or “PI-DC”, answers some fundamental questions that every digital (or analog) designer should ask and answer:

  • Have I provided enough metal between my sources and loads to deliver adequate voltage to every load?
    • Enough power and ground shapes
    • Enough vias, and are they large enough?
  • Can I cleverly optimize my PDN shapes?
  • What part of my design is most likely to heat (burn) up?
  • Have I done something weird with my ground shapes?

Many digital designers are aware of the need for accurate signal integrity analysis, or how essential it is to understand the AC aspects of their PDN (“How many decoupling capacitors do I need?”, for instance), but give little regard to their DC PDN (“PI-DC”) analysis. PI-DC analysis is also critical, however, since it can provide critical insight into a design’s quality and save valuable design real estate and layers, ensuring a cost-effective digital design. The fundamental question it answers is relatively straightforward – have I provided enough metal (in our case, almost exclusively copper) between my power source and all the loads to deliver adequate power to those loads? But, in today’s world of small, integrated designs, answering that question accurately can mean the difference between success and failure.

Those days are gone...

Not long ago, digital design was dominated by large form factors – desktop personal computers and large servers, for instance. In those designs, entire metal layers could be dedicated to power delivery, ensuring minimal voltage drop between the source and loads. Conservative rules of thumb could be used to estimate how much metal was needed with little consequence if more than enough area was dedicated to power delivery. A digital designer only ensured the DC power delivery was “adequate,” with little thought about optimizing the power delivery shapes to minimize their area and layers.

Those days are gone – even server designs are becoming incredibly dense and board real estate is a valuable commodity that can’t be wasted with overly conservative design practices. Now all metal dedicated to power delivery must be “necessary”, we don’t have the luxury of additional layers or board size. PI-DC analysis provides a sophisticated means of ensuring the power delivery metal is not only adequate but necessary.

And the answer is?

It has become clear that the only way to accurately analyze and resolve the most complex PDN issues required a dedicated analysis tool within the engineer’s design workspace. Download our free whitepaper now to learn more about the benefits of adding a PI-DC analysis tool to your existing digital design toolbox. 

About Author

About Author

Signal and Power Integrity Product Manager at Altium
Jeff Loyer is the Signal and Power Integrity Product Manager at Altium. Prior to joining Altium, he spent more than 20 years as an engineer at Intel, the last 10 as signal integrity lead for their server divisions. While at Intel, he led work groups which significantly impacted the industry’s high-speed PCB design practices, including work on the Fiberweave Effect, copper roughness, environmental effects on insertion loss, and insertion loss control and measurement (inventor of SET2DIL).

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