DDR Layout Tips to Maximize Signal Integrity of Complex Memory Devices
The science of transporting people by air has changed dramatically in a very brief period of time. During the 1920s, the Ford Trimotor was considered the ultimate luxury flight experience. Affectionately known as the “Tin Goose,” the first all-metal, multi-engine airliner could comfortably carry 10 passengers on a 36-hour transcontinental flight.
When we consider modern passenger aircraft, the concept of moving people comfortably over long distances remains the same. However, technological innovation has spurred design changes and caused design teams to rethink how aircraft should fly and look. Boeing 787 passenger aircraft feature a digital fly-by-wire design built through concurrent engineering, 2.3 million, and the use of lightweight carbon fiber reinforced composites.
Complex System Design Lives within DDR
The “Tin Goose” and Boeing 787 represent milestones in complex system design. In the same way, computers changed dramatically as processor and memory technologies improved. During the mid-to-late 1980s, everyone loved Intel for its 80386 processor. Individual memory chips populated circuit boards that plugged into a motherboard. As we literally flash forward to today, Double-Data-Rate (DDR) memory increases data transfer speeds while reducing power consumption by doubling data throughput in one clock cycle. Synchronous data strobes capture data on both the rising and the edges of the strobe and improve data bus performance. With the introduction of the fourth generation DDR4 memory, we have also observed improved data integrity and higher chip densities.
Increasing the capabilities and complexity of memory devices dramatically impacts PCB design. In particular, any issues involving signal integrity and timing require more attention. For example, you should place DDR signals on ground-referenced critical layers to achieve the lowest possible impedance for return currents. Each of those layers must remain solid and continuous. With the same goal in mind, avoid crossing split power planes with DDR signals. Following those practices improves signal integrity performance.
Especially with complex devices, checking and testing couldn’t be more important
PCB Design With Component Interaction
Boeing’s Dreamliner design considers the coordination and implementation of thousands of interacting components. The same coordination of interacting components occurs on a smaller scale within PCB design.
DDR memory controllers consist of more than 130 signals that divide into the clocks, data, address/command, control, and feedback signal groups. Clock signals establish the timing of the data input and output signals moving to and from the DDR memory. Proper operation of the DDR device depends on the precise arrival of the clock signals and a prescribed amount of setup and hold times.
Because each bit of the data bus must arrive and become stable before the clock cycle, the clock signals establish setup time for accepting or extracting the data. The hold time ensures that the entire bus remains steady during the read-in or read-out after the clock.
Using your routing to build in delays works as one method for maintaining the precise timing of the clock signals. Use your design tools to manipulate the trace length to achieve the desired delays and timing. To accomplish this manipulation, specify the timing requirements for the clock signal.
Ford’s Trimotor used corrugated metal skin to obtain stiffness but sacrificed performance. To obtain proper optimization, you should follow the sequence shown in table one for routing the signal groups within the DDR memory channel. Of the groups, the data group has one of the higher priorities because of the faster clock speed for the data bus and concerns about signal integrity. The data group also uses the largest amount of space on the data bus.
As you begin the PCB layout, using DDR memory requires that you precisely match trace lengths, have stable voltages, and apply proper termination. In addition, you need to institute basic good practices such as maintaining optimum operating temperatures and proper setup and hold times.
Matched Trace Lengths Result from Good Systems Engineering
In less than 100 years, systems engineering practices like traceability and interface management prompted the leap from the Ford Trimotor to the Dreamliner. Using DDR memory requires trace length matching for specific routing groups because of the dependence on precise timing relationships. Use the absolute routed maximums to prevent signal integrity problems.
All signal groups have a relationship with the clock signal while data signals have an additional relationship with the strobe. When building your PCB design, recognize the need for trace length matching within the Clock-to-Address/Command group (CLK/ADDR/CMD), the Clock-to-strobes (CLK/STB) group, and the Strobe-to-Data Group (STB/Data). In turn, those relationships rely on timing margins and delay lengths specified by manufacturers. While the trace lengths of clock signals must match the trace lengths of the address and command signals in the CLK/ADDR/CMD group, the CLK/STB and STB/Data groups impact data timing.
Don’t hesitate in addressing signal integrity demands.
Keeping Things Stable
When we consider traditional semiconductor technologies, all require stable supply and reference voltages, regardless of loading, power supply variations, or temperature changes. In extreme cases, current or voltage levels that exceed device limits cause electrical over-stress and thermal damage. DDR memory is no different in that it requires stable supply and reference voltages.
Any reference voltage variation affects signal integrity and the ability to reference signals to trigger correctly. Noise or changes in the input reference voltage (VREF) causes timing errors, unwanted jitter, and erratic behavior throughout the memory bus. When planning your layout, place the VREF and the termination voltage (VTT) on different planes to avoid the VREF buffer sensitivity to the termination plane noise. The reference voltage and the termination voltage must share a source supply.
Your layout should allow a 20 to 25 mil trace width for the VREF voltage. In addition, maintain a 20 – 25 mil clearance between the VREF voltage and other traces to maintain VREF isolation. Use distributed and balanced decoupling to localize transient currents and returns.
Keeping track of power supply and voltage variation can be challenging but with PCB layout software like Altium Designer®, you can ensure that your PCB signal integrity is not compromised. Talk to an Altium expert if you’re interested in more tips on DDR layout or want to learn more about Altium.