DDR3 Memory Interfaces and Topologies in PCB Design

Created: August 28, 2018
Updated: September 25, 2020

Futuristic gear on gray cyber background

In the World Memory Championships, individuals compete in memory sports by memorizing as much information as possible within a specific timeframe. The championships include ten different disciplines that cover numbers, binary digits, playing cards, random lists of words, names and faces, historic dates, abstract images, and speed cards.

No one has tested the World Memory Champion against DDR3 memory and no one really knows how the World Memory Champion processes information. We do know, however, that double data rate (DDR) memory devices transfer data on both the rising and falling edges of the clock signal. This involves moving information really fast at a maximum transfer rate of 14.9 gigabytes per second.

Do You Remember When…?

PCB Designs use DDR3 memory because of its low power, high signaling speeds, and large bandwidth. Because a DDR memory subsystem includes the controller, PHY, and IO, it serves as a critical component of the System on Chip (SoC) designs used in cell phones, high-definition televisions, and other consumer electronic devices. Small, fast-memory DDR memory devices lower device footprint as well as the overall cost of the consumer device. While those devices are being operated, the processor in a SoC uses most of its cycles to read and write to DDR memory. Consequently, any problems that occur within the DDR memory subsystem wreak havoc with the operation of the cell phone or television.

DDR Interface Data Signals

DDR memory uses source-synchronous interface data signals. The memory and controller capture the data using the data strobe rather than the clock signal. When a data transfer occurs, the process uses both edges of the strobe to achieve the higher data rate.

Interdependent factors such as PCB layer stackup, delay matching, crosstalk, impedance, and timing affect the signal integrity and delay in circuits that feature DDR3 memory. The performance of the devices depends on delay matching. In turn, timing requirements control delay matching. Your PCB design includes a timing budget for DDR3 memory interfaces. The timing budget includes the:

  1. Double data rate Data Write for the input/output data (DQ) and data mask (DM) to the data strobe and data strobe at active low (DQS/DQS#)
  2. Double data rate Data Read for the DQ to DQS/DQS#
  3. Single data rate Address and Command to Clock (CK/CK#)
  4. Single data rate Control to CK/CK#
  5. Cross-domain for the CK/CK# to DQS/DQS#

For DDR3 circuits, you must ensure that the design meets delay matching requirements.

DDR3 Routing guidelines

When designing your PCB, route the DDR memory channel in the order of Data, Address/Command/Control, and Clocks. With the Data group operating at twice the clock speed, maintaining signal integrity becomes the highest priority. Because Address/Command/Control has a relationship with the routed clock, the effective clock lengths satisfy multiple relationships.

Given the requirement for signal integrity, you should route each data lane adjacent to a solid ground reference for the entire route. With this technique, the route provides the lowest inductance for return currents and optimizes signal integrity.

As you route the byte lanes, always route the signals within a byte lane on the same critical layer used for connecting the PCB motherboard to memories. Routing the signals in this way minimizes the number of vias per trace and establishes uniform signal characteristics for each signal within the data group. In addition, alternate the byte lanes on different critical layers to keep the signals together and ease the break-out from the controller.

Trace spacing on Altium ’s 3D viewer

Finding out minimum trace spacing is important for your memory routing

Use the Fly-by Topology

Fly-by topology connects DDR3 chips located on a memory module in series and provides an increased noise margin. Fly-by routing daisy chains the clock and addresses control signals along the length of the DIMM. A grounded termination point at the end of the linear connection prevents residual signals from reflecting back along the bus by absorbing the signals. The topology also provides matched loading on all signals within a rank.

When you use fly-by topology with DDR3 memory, you gain a faster slew rate for the signal. In addition, the topology supports high-frequency operation. Because the topology reduces the quantity and length of DIMM slots or stubs, it improves signal integrity and timing on heavily loaded signals. The improvement occurs because of the reduced reflections from each stub.

Avoid Simultaneous Switching Noise

DDR3 memory devices can have problems with simultaneous switching noise or SSN. The noise occurs when a driven signal within the chips transitions across states and consumes power from the rail. When many signals switch simultaneously, the rail can droop due to the lack of charge needed to immediately provide current for switching outputs. The decrease in rail voltage can result from a layout that results in high series inductance for capacitors in the power distribution network and can cause the drivers to push signals that include noise. As a result, switching one signal essentially changes the output of another signal.

Screencap of Altium ’s auto-interactive routing

Make sure you have the software that can help you check your EMI.

Try Read-Write Levelization

Fly-by topology reduces SSN by introducing flight-time skew between the address group and point-to-point topology signals of the data groups. Then, the topology matches the timing between the DQS and the clock through a technique called Read-Write Levelization that occurs between the PHY and controller of the device.

During writes, levelization staggers the launch of the DQS signals so that the signals arrive coincidentally with the clock. Staggering the signals delays the launch of the last byte, causing it to arrive at the same time as the clock as it routes on the DIMM. Read levelization compensates for the different launch times from the fly-by clock. During Reads, levelization uses the launch of the DQS signals so that the signals align with the controller of the device.

Altium Designer®  provides robust tools for creating DDR3 memory groups. With Altium , you can use the project’s schematic and place a blanket around nets used for groups. You can also effectively plan for routing and CDU DDR3 fanout.

To learn more about using Altium to develop DDR3 memory interfaces, talk to an expert at Altium.

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