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How to Route DDR3 Memory and CPU fan-out

Robert Feranec
|  Created: February 21, 2017  |  Updated: November 4, 2020
How to Route DDR3 Memory and CPU fan-out

It's becoming more and more inevitable that board designers have to do high edge rate (high speed) PCB designs when working with microcontrollers. With the power of CPU's like the Freescale iMX6 multi-core ARM device family, but at very low "cost per MIP", it's more and more desirable to use devices like this to enable rich software and user experiences in your product.

But using these super-micro added memory controller bears with it the challenges of high speed, dense memory interfaces with DDR3 layout guidelines. In this guest blog, Altium Designer user Robert Feranec of Fedevel Academy shows us some highly valuable tips on routing DDR3 memory, based on his open-source hardware design of the iMX6 Rex, a compact and powerful Single Board Computer development kit. 

DDR3 memory is so pervasive; it’s almost inevitable that professional printed board designers will face a board they must route using it. This article gives you tips to properly fan-out and route DDR3 memory interfaces, even in very high density and tightly packed PCB layout.

DDR3 Memory Design Rules and Signal Groups

Everything starts with the recommended high speed PCB design rules for routing DDR3 in groups. During DDR3 memory layout, the interface is split into the command group, the control group, the address group, as well as data banks 0/1/2/3/4/5/6/7, clocks and others. It is recommended that all the signals which belong to the same group should be routed “the same way” ie using the same topology and layer transitions.

Using topology and layer transitions

Figure 1: All signals in the DATA 6 Group are routed “the same way”, using the same topology and layer transitions.

As an example, consider the DDR routing sequence shown in Figure 1. All the DATA 6 group signals go from Layer 1 to Layer 10, then to Layer 11 and after that to Layer 12. Every signal within the group makes the same layer transitions and generally takes on the same routing distance and topology.

One of the advantages of DDR routing the signals this way is that during length tuning (a.k.a. delay or phase tuning) the z-axis length in the vias may be ignored. This is because all the signals routed the same way will have exactly the same via transitions and lengths through vias.

Creating DDR3 Memory Groups

Altium Designer® supports a simple way of creating the necessary signal groups and watching for signal integrity. This step is done in the project’s schematic. First, a blanket is placed around each set of nets that groups are being created from. Then a net class printed board directive is attached to the edge of the blanket to apply a net class to the group. An example of this is shown in Figure 2.

ddr3 memory example tutorial

 Figure 2: Blankets and PCB directives are used to create net class groups for DDR3 routing guidelines.

Assigning Colors to a DDR3 Memory Group

After we import the new Net classes to our printed board (through the Engineering Change Order (ECO) underDesign » Update PCB Document...), it is very useful to assign different colors to each group, to make routing easier to mentally follow. Go to the printed board panel, right-click on the group (net class) you would like to assign a color to, and choose Change Net Color from the popup menu, as shown in Figure 3.

ddr3 interface example

 Figure 3: Assigning different colors to each group can make routing easier to mentally follow.

Once you have chosen a color, right click on the net class or net again and choose Display Override » Selected ON. This ensures that the net color you selected overrides the layer color of whatever layer is currently used by objects of that net.

If you haven’t turned on the Net Color Override, the nets will not have the color you selected. In this case, press toggle the View » Net Color Override option or use the F5 key to enable this setting globally (for all the nets). Now you are ready to fanout the DDR3 interface of the CPU.

Do You Plan Ahead When Working on CPU DDR3 Fanout? 

Choosing the correct via style for a particular memory group and deciding on how PCB layers will be used can make DDR3 layout a lot easier. Assigning different colors to each memory group helps to visualize the interface.

CPU memory interface

Figure 4: Choosing a correct via size can help save space for more tracks.

A microvia (μVia) takes less space compared to a Through Hole Via. This allows us to fanout more tracks in the same area. Microvias also save space on the other layers. The free space can be used for tracks.

Why Use Microvias for Address, Command, and Control Signals?

The Address, Command, and Control group have the highest number of signals from the memory groups. If we chose Through Hole Vias, we would use a lot of space on all the layers. By choosing microvias, we only need the space on Layer 3 and because a microvia is smaller in diameter, we also have more space to fanout the signals on Layer 3.


Figure 5: Two or three tracks can fit between microvias, in the same space needed for one track between Through Hole Vias.

Why Use Through Hole Vias for the “Closest Groups” to the Address, Command, and Control Group?

Some signals of the Address, Command, and Control group will need the space below the “closest groups”.

Closest Groups

Figure 6: Some of the Address, Command, and Control tracks have to be routed under the pads of the “closest groups”.

When the Address, Command, or Control signal group is routed through microvias on Layer 3, there will be free space left under this group on Layer 10. This space can be used to fanout the “closest groups”.

Microvias and fanout

Figure 7: Free space left under groups routed with microvias can be used to fanout the “closest groups”.

Why Do the “Outside Groups” Use Microvias?

From the picture above, it’s clear that there will not be space left on the Layer 10 to fanout the “outside groups”. So placing the “outside groups” on layer 3 and using microvias is the result of the fanout planning.

Note: The same Layer / via / microvia “fanout planning technique” can be applied on the other interfaces too (e.g. PCI, ISA, … ). This way, even really packed and very dense designs can be routed.


By a bit of care and planning ahead, routing and length tuning DDR3 fanouts can be a stress-free process, even on the most compact and densely packed design guidelines. The iMX6 Rex is a terrific example of this care and planning, designed in part as a tool for showing how it’s done. By following Robert’s plan and steps any DDR3 design can be completed in far less time and with much greater likelihood of designing it right the first time. 

See more Altium Designer projects or find out more about what PCB designers need to know about DDR5 here.

About Author

About Author

Robert Feranec is the founder of FEDEVEL Academy and throughout his career, he has designed motherboards based on Intel, AMD, and VIA processors. He holds a B.Sc and M.Sc in Electronics and has worked as a Hardware Design Engineer at notable companies like VOIPAC and EUROTECH where he helped develop voiceover IP systems and industrial computers.

Robert is very well known through his YouTube channel, instructional videos, and Udemy courses where he teaches various Hardware Design courses. He also runs several successful open source projects and regularly contributes to electronic enthusiasts and professional communities by sharing his knowledge through free videos, blogs, and forum posts. Robert is currently living in Europe where he focuses on teaching hardware design.

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