See What’s Coming Soon to Altium Designer 24

Setting the new standard in electronics design.

Designing Your Circuit Board for Boundary Scan PCB Testing

Zachariah Peterson
|  Created: May 28, 2019  |  Updated: April 21, 2020

Manually testing a PCB with an oscilloscope

You can avoid some manual circuit tests with a boundary scan test

On simple boards with few components and surface-level traces, you can probably test all aspects of your board by hand without much difficulty. Imagine you needed to do this with a multilayer PCB, and you’ll see that there are many aspects of a manufactured and assembled board that cannot be tested by hand.

With more advanced boards, where traces are embedded in the interior layers and ICs might be soldered onto BGAs, there is no way to connect multimeter leads to conductors and take electrical measurements. You’ll have to hope that there are no physical faults and that the components themselves are operational after manufacturing. Enter the boundary scan test: this testing methodology allows you to diagnose physical faults without placing multimeter probes on every test point on a PCB or IC package.

JTAG and Boundary Scan Tests

Procedures and architecture for boundary scan tests in embedded systems are codified in the Joint Test Action Group (JTAG), which is the common name for the IEEE 1149.1 standard. This is a hardware interface that allows chips on a board to be tested using a set of specific test signals. Ever since it was developed for Intel’s 80486 microprocessor, it has become the standard for programming and debugging all embedded systems and devices.

The goal in these tests is to identify faults in an IC package like CPLDs and FPGAs. The required test logic to verify all functionality is contained in the IC itself, and limiting the actual interface is limited to a small number of manageable inputs. Designers that want to eliminate some manual post-manufacturing testing procedures and expedite field testing can incorporate a JTAG-based testing and fault diagnosis system at the PCB level.

Aside from testing the electrical functionality of ICs, boundary scan testing is important at the PCB level for diagnosing physical faults in interconnects. This allows physical faults like pads, pins, and soldered BGA connections to be diagnosed for failure. In fact, testing of devices mounted on BGA was one of the forces that helped popularize JTAG testing. Once an IC is soldered to its BGA, the solder points cannot be tested manually, leaving costly X-ray inspection as the only option to diagnose physical faults on an interconnect involving a BGA connection.

Passive and active components on a green PCB

A boundary scan test is the best way to identify failure points in this PCB

Designing for Boundary Scan Testing

Before you start laying out components in consideration of boundary scan testing, you should try to select IEEE 1149.1 compliant ICs as these components are designed to allow boundary scan tests. A test bus connector should also be placed at the edge of the PCB. If your board is a card with an edge connector, you can also route test bus signals to any spare pins on the edge connector for easier accessibility in a multi-board system.

Components with JTAG test access ports (TAPs) are normally laid out in a daisy chain along the length of the test bus. If possible, it helps to layout each component so that TAPs face the test bus in order to eliminate the use of vias. You’ll need to route any traces along the test bus so that signal reflections are eliminated, which might require creating designing a termination network for some components. You should also suppress overshoot with a series resistor along a trace to critically damp signals in the test bus.

When devising a boundary scan test for an FPGA or CPLD, different tests will need to be performed before and after the device is programmed. Once it is configured, some of the I/O pins may switch from input to output only, and some single-ended I/O pins may be grouped into differential pair I/O pins. The component manufacturer normally supplies a BSDL file that specifies the appropriate boundary scan procedure, so you will need to design a new BSDL file for the configured device. The same software you use for CLPD or FPGA design should allow you to generate a BSDL file for the programmed component.

ASICs and passive components on a PCB

Including TAPs alongside ICs allows for a full boundary scan test

Why You Need to Implement Boundary Scan Test Design

If you’re in the prototyping phase and need an easy way to diagnose potential problems in your board, then you need to design your board for boundary scan testing. This is especially important for boards that will be used in harsh environments, or if you are performing physical durability tests. The ability to diagnose physical faults allows you to identify failure points during testing and redesign as necessary.

If you’re designing a board that might require field repair, or you want your new board to be amenable to a forensic boundary scan, then you need to include these features in your design. This will allow you to identify failure points later in the product lifecycle, giving you greater insight into potential redesigns.

Whether you want to implement purely physical testing features for simpler boards or far-reaching boundary scan testing capabilities in a more complex design, Altium Designer® contains the design and layout features you need to make it happen. The FPGA design tools allow you to generate the BSDL files you need for automated testing.

If you’re interested in learning more about Altium Designer, you can download a free trial and get access to the industry’s best layout, routing, and simulation features. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

Related Resources

Back to Home
Thank you, you are now subscribed to updates.