One of the early differential signaling protocols used for serial communication was low-voltage differential signaling, or LVDS. Throughout the development of standardized protocols and interfaces, there have been many standards that have come and gone. LVDS started as an excellent general purpose high-speed digital communication standard, and it still sees such use to this day. As a differential communication standard, it brings some signal integrity and EMI benefits as long as certain requirements are met.
This article will provide a basic overview of LVDS routing requirements in a PCB, as well as some innovative use cases of LVDS routing for parallel differential interfaces. If you have never worked with an LVDS interface before, these guidelines will tell you what you need to verify before you create LVDS design rules and route your differential pairs.
As a differential interface, LVDS follows the standard set of differential pair design guidelines to ensure signal integrity:
Again, LVDS just uses a differential pair linking a driver and receiver; there is no limit on trace width and spacing other than what is manufacturable as long as it meets the differential impedance requirements.
At its core, LVDS consists of a differential transmitter and differential receiver with DC reference voltage, so LVDS measures the difference between non-inverting and inverting signal levels about a common-mode DC offset voltage. This DC offset is 1.2 V (typical for devices powered with 2.5 V, 3.3 V, and 5 V I/O supplies), although some standards like sub-LVDS use a lower 0.9 V offset to ensure compatibility with 1.8 V I/O supplies.
The main LVDS architectural elements include:
In terms of the signal behavior, LVDS uses a +/-175 mV swing about the common-mode DC offset voltage to define logic levels; this low voltage swing is the reason for the protocol's name. The LVDS driver operates with a 3.5 milliamp push-pull mode current source, with each line in the differential pair carrying current in opposite directions. When terminated to the target 100 Ohm impedance, the injected current develops +/-350 mV across the receiver's pins.
A few points to note about signal integrity in an LVDS link:
The ground offset factor is typical of all differential pairs as the interface eliminates the common-mode DC offset voltage, even in the case where offsets are quite large. In terms of LVDS with a 1.2V common-mode DC offset voltage, this means an LVDS receiver can operate within a DC offset ranging from 0.2V to 2.2V. This makes LVDS ideal for applications where driver and receiver may be on different boards with separate power supplies and floating grounds.
As differential pairs with bandwidth reaching only a few GHz, LVDS is quite easy to design and route. Design the link to the required impedance and use a ground plane, and beyond this there is not much else to worry about.
Some myths that should be addressed surrounding the use of LVDS include:
The image below shows a Texas Instruments reference design that uses multiple LVDS lanes for communication between a set of RF ASICs and an FPGA. In this example, specialty logic is implemented in the ASIC such that one of these lanes is a clock lane, while the other is a data lane. You'll notice that the traces in each LVDS differential pair are delay-matched to each other as would be expected in a parallel interface.
Example delay-matched LVDS lanes (1x clock, 1x data)
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