When design engineers started using simulation toolsets, we originally cared only about impedance and terminations. Then when things got fast, we had to worry about loss in the path. Next, we had to address differential pairs (which are specialized transmission lines) and skew. Most recently, we have had to worry about the effect of vias at very high data rates. Note: Of all of these elements, skew is the only one which cannot be simulated. From the overall product development process, signal integrity analysis needs to take place before the schematic is drawn in order to determine if what is being proposed is feasible from both the design and manufacturing process perspectives. And, the simulation process helps us make this determination.
In previous articles, I have discussed how differential pairs are designed and simulated and I have also addressed power delivery simulation. This blog will take a look at two of the most common elements associated with simulation—impedance and crosstalk and will describe the basis of these two factors, how they are simulated and the challenges associated with them. Part 1 of this blog discusses impedance control while part 2 will address crosstalk and its impacts.
Just to review, impedance is the resistance that a transmission line presents to the flow of energy along that transmission line. There are two areas where impedance comes into play: the design process and the fabrication process. During the design process, the product developer needs to satisfy two questions—is the transmission line impedance manufacturable, and does it meet the design goals. Figure 1 shows a schematic representation of a transmission line with all of the elements that are involved in determining the impedance of a transmission line.
Figure 1. Schematic Model of a Transmission Line
As shown in Figure 1, impedance is composed of three parasitic elements:
At DC or low frequencies, parasitic resistance is the primary determining factor in transmission line impedance. When designs intended to handle DC voltages are created, only parasitic resistance is used to calculate current flow. For these types of designs, both parasitic inductance and capacitance can be ignored because their effect is not noticeable. As the frequency gets higher than a few kilohertz, the reactance of the parasitic inductance tends to block or impede that flow of energy. At the same time, the parasitic capacitance tends to shunt the energy to “ground” or the plane. These two elements work together in such a way that a constant impedance is seen by the electromagnetic field at all frequencies.
Equation 1. The Impedance Equation
Equation 1 can be used to calculate the impedance of any transmission line. All that is required is a method for determining Ro (parasitic resistance in ohms per unit length) Co (parasitic capacitance in farads per unit length and Lo (parasitic inductance in henrys per unit length). The key factors to keep in mind when determining the impedance of a transmission line are:
The impedance of a transmission line is not a function of its length.
The impedance of a transmission line is not a function of frequency.
As long as the cross section does not change, the impedance will be the same whether the line is
1 cm long or 1 km long.
As long as the dielectric medium has a dielectric constant that is constant with frequency, the impedance will be constant, no matter what the frequency.
When all of these factors are taken into account, simulating the impedance of a transmission line is a straight-forward and fairly easy process.
It’s important to note that, with very few exceptions, the impedance of a transmission line is going to be 50 ohms (100 ohms differential). At times, there has been a move afoot to try and ascribe a transmission line impedance other than 50 ohms. For instance, in the PCI bus specification, there are several impedances within the PCI Express document that do not follow the 50-ohm guidelines and they are all arbitrary. The PCI bus specification is 65-ohms (the reason for this is described in my blog, “Why is the PCI Bus Specification 65 Ohms?”). Further, this document suggests that there should be 85-ohm differentials instead of 100. It is also stated that the USB impedance should be 93 ohms +/- 15% (which gets you to 100 ohms anyway). If you are designing a four-layer PC motherboard, the 65-ohm requirement is not too big of a deal. But, since the PCI bus is often included in big designs that contain hundreds or thousands of nets, making enough room for such a large number of nets will require many signal layers that have to be buried microstrip or stripline layers. It’s very difficult to create a PCB that is comprised of these types of layers and has more than one impedance and have the right amount of space for each different impedance.
Once an impedance has been determined and the PCB geometries decided, it’s time to start the simulation process. Note: With parallel terminations, no simulation is required. It’s simply a matter of selecting the termination resistor value to match the impedance of the trace. With series terminations, you need to get the driver you propose to use and then see what series termination is required.
Following these steps, the dimensions of the PCB need to be factored in. This includes both the trace width and the height of the trace above the plane. There are a number of commercially-available simulation tools that can be used during this process.
Errors can occur during the stackup process in terms of layers being inserted in the wrong order or prepregs being inserted incorrectly. These errors can be difficult to detect without special test structures. One approach is to build test coupons that accompany the PCB throughout the manufacturing process. These coupons are used to verify impedance, stacking and plating quality. As coupons can be lost in the process and the correlation of impedance in the coupon to the PCB can be difficult to implement, we instead recommend that test structures be built into the PCB. In the test structure for impedance testing there is a collection of impedance traces; one for each layer that has impedance control. We recommend the use of these test structures for all high-speed PCBs. Talk to an Altium expert today to learn more.