How to Design High-Density PCBs While Managing Buried and Blind Vias

Zachariah Peterson
|  Created: April 5, 2017  |  Updated: February 16, 2026
How to Design High-Density PCBs While Managing Buried and Blind Vias

So you’ve increased the component density in your PCB so high that you can’t use through-hole vias for routing. Now what?

The solution is inevitably blind and buried vias, with most of the routing occurring on inner layers. Situations with large overlapping ICs, overlapping BGAs, BGAs overlapping with large arrays of discretes, and many other situations can force the use of blind and buried vias. At minimum, these are needed in BGA fanout regions, but they can technically be used anywhere the board space allows.

Getting this correct, and not losing track of routing layer assignments, manufacturability rules, and predefined drills, requires some front-end engineering. If some upfront work is completed first, your design is much more likely to avoid engineering questions or no-bid status before production. We’ll run over these tasks in this guide, so make sure you complete these tasks before starting to route the board.

How to Keep Track of Your Blind and Buried Vias

Mechanical or Laser Drilled?

When most new designers hear about blind and buried vias, they probably go straight for HDI design, where vias are laser drilled in thin layers on the outside of the stackup. However, it does not have to be this way. Blind and buried vias can be mechanically drilled, but the process imposes additional constraints due to the plating process and finished copper weight.

Therefore, the first thing to do is decide whether the vias will be mechanically drilled or laser drilled. This will limit where you can route and how signals get there, as well as the feature sizes you can implement.

Mechanically-drilled blind/buried vias

Laser-drilled blind/buried vias

  • Aspect ratio: Limited by drill diameter (at least 8:1 typical)
  • Aspect ratio: Limited to <1:1 based on specific build-up film material
  • Smallest drill: 6 mil/0.15 mm
  • Smallest drill: <4 mil/0.1 mm

With laser-drilled microvias, reliability qualification is needed either by the fabricator or your team in the intended deployment environments. Read this older article from Happy Holden, the godfather of HDI, to learn more about microvia reliability.

Build the Right PCB Stackup

All via transitions have to conform to the manufacturing constraints imposed on PCB stackups. The stackup is where you will plan these transitions based on the fabrication process that you have selected. This requires knowing the three standard approaches for building PCB stackups with blind and buried vias:

  • Sublamination builds for mechanically drilled blind/buried vias
  • Sequential lamination builds for laser-drilled microvias
  • A combination of the two processes

The most important reason for understanding the build process is knowing the resulting plating requirements during buildup. When blind vias start on the same layer in a sublamination, that layer will be plated repeatedly, and that will force growth in the copper weight during stackup fabrication. This means if you start with a 1.0 oz per square foot copper film, the final weight after multiple plating cycles might be much larger than 1.0 oz after the plating cycles have completed. This is due to the stack-drill-plate procedure when fabricating sublaminations with mechanically drilled blind/buried vias.

For this reason, when selecting where to place blind/buried vias, consider limiting the number of vias starting or ending on the same layer. As the copper weight grows, it limits the etch feature size to larger values. On internal layers, this is manageable, but multiple blind vias starting on the same external layer limit your ability to pack components close together and perform fanout routing.

 

Pick a Padstack and Stick With It

Once your technology is selected and you have determined the smallest allowed drill diameter for your stackup and any sublaminations, you should figure out the padstack you want to use and not deviate from it. There’s good reason for doing this, primarily that the routing tools in a PCB editor will allow you to use any padstack you like. However, you want to ensure that you comply with DFM constraints on your drills and annular rings. Picking a padstack for your blind and buried vias ensures that you’re always complying with the DFM constraints imposed by your stackup.

Another reason to pick a single padstack for your blind and buried via transitions and stick with it is that it simplifies your fabrication documentation. Simplifying the tooling list and your documentation reduces NRE costs, per-board costs, and reduces the chances of errors. Whether you’re producing small prototype runs or building boards at volume, all of those factors are beneficial.

Simplifying fabrication documentation also helps you stay sane as a designer. It’s easier to track what’s happening in your drill drawings, review CAM files, and resolve technical questions from fabrication.

Multiple sets of drill data will be needed for each of the via transitions defined in the PCB stackup.

To limit your allowed via types or padstacks, you can use padstack templates or net/net-class-specific design rules. Either approach is very easy to configure in Altium Designer.

Specify IPC Via Types for Via-in-Pad

Via-in-pad is typically the use case for blind and buried vias, specifically for mechanically drilled vias. When planning your routing, you should determine which of your vias will be filled and plated, as not all vias will need this treatment.

There are several ways to do this, but not all of them are very good:

  • Create a mechanical layer which indicates the sets of blind vias to be filled and capped
  • Apply filling and capping to a specific padstack or layer transition
  • Create a separate bill of materials table entry and/or drill drawing for filled and capped blind vias
  • Assign filling and capping as a property to specific blind vias, i.e., as a specific IPC-4761 via type

Altium Designer is unique in that it allows users to perform all of these methods for indicating blind and buried vias which specifically need via-in-pad.

When defining a via in Altium’s PCB editor, users can select an IPC-4761 via type for each via in the PCB layout. Once these are selected, relevant data can be exported from an auto-generated mechanical layer as Gerbers or included in a smart data output format, such as ODB++ or IPC-2581.

Whether you need to build reliable power electronics or advanced digital systems, use Altium’s complete set of PCB design features and world-class CAD tools. Altium provides the world’s premier electronic product development platform, complete with the industry’s best PCB design tools and cross-disciplinary collaboration features for advanced design teams. Contact an expert at Altium today!

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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