PDS Design For Ultra-low Power Implementations

Kella Knack
|  Created: May 13, 2019  |  Updated: April 17, 2020

When it comes to low power implementations, products are characterized as very rarely having high current options, being small in size, being optimized for power management and having the necessity for batteries to last as long as possible. There’s a broad spectrum of products that fall under these criteria including, but not limited to, smartphones, smartwatches, remote monitoring devices and medical devices to name a few.

In terms of PDS design and power management, there are a few main factors that are inherent in every product that is characterized as being ultra low power: designing efficient PDSs in very small geometries, managing power consumption and conserving battery life. In some product implementations, such as remote monitoring devices, selecting the right capacitors to eliminate them as potential sources of power drain (due to leakage) is also a critical factor. This article focuses on these dynamics.

If you haven’t read it yet, this blog focuses on the evolution of PDS designs, the challenges associated with them relative to where power flows, and the impact of inductance and resistance in terms of performance degradation and is a good place to start exploring Power Delivery Systems.

So Much Functionality in Such Small Products

Smart technology, implemented in small form factors, has become so ubiquitous in our daily lives that it’s difficult to imagine when we did not have it. And, the evolution and sophistication of the technology contained within these devices has improved by such leaps and bounds that we have become cavalier in terms of what it takes to implement and operate the various product features upon which we have become so dependent.

For example, the technology that comes into play when you rotate your phone from vertical to horizontal such that the screen remains in alignment, is what we used to refer to as a supercomputer. And there are so many features in a smartphone—a few radios, one or more cameras, the screen, the processors inside, and the memory—that consume power, making it a challenge to manage all of the various power zones. It’s important to remember that for every power rail in a device there is a PDS and it is not uncommon to have 15-20 PDSs in a smartphone.

Thus, the main job for a PCB designer comes down to figuring out how to have enough regions on the boards for each power rail, and how to find enough ways to segment the planes when you don’t have that many to start with.

For instance, the iPhone 10 (iPhone X) has two very thin PCBs. One is eight layers while the other is ten. Both boards have components on both sides and the two boards sit on top of each other inside the phone. The complex ICs have no packages on them at all, they are all bump die. (Bump die are also known as Flip Chip or controlled collapse chip connection (C4). It’s a method for interconnecting ICs to external circuitry with solder bumps and it allows for connecting ICs to boards in a very small area).

And, because of these tight geometries, there is no room for having plane capacitance as a way of managing the PDS. All of the capacitance is built directly into the ICs. In actuality, the design expertise that is required for developing these products has become very specialized and is very different from traditional PCB design.

Power Management

So, we have two of the parameters for ultra-low power products accounted for—lots of functionality in a very small space and a number of PDSs in any one device. In terms of power management, a cell phone is architected such that when a particular function is not being activated, it is turned off. And, that’s where getting the PDS operation nailed down is crucial.

As a designer, you have to figure out how to manage all of the major power consumers within a phone such that they turn off and on at the right time. In most smartphones, the biggest consumer of power is the radio. When you are uploading videos, pictures, large amounts of data, etc., the radio is on continuously and the power consumption is high. In the mid to low power usage range, there is text messaging and uploading of simpler data files. At the extreme low end of power usage is the “pinging” that takes place between your mobile device and a cell phone tower that continuously monitors your location. In essence, the only time your cell phone is not consuming power at some level is when it is completely powered down.

Battery Conservation

Next, we come to what is probably the most important aspect of ultra-low product implementations: making the battery last as long as possible. For smartphones, battery life is an important feature but for other products such as remote monitoring devices, power conservation is an absolute necessity. An example of this type of product would be a power line monitor which is clipped onto big transmission lines. In most instances, the performance requirement for these devices is such that the batteries have to last at least a year. But, if the capacitors are of the wrong type, they can leak and the batteries will be discharged far sooner than desired. 

Theoretically, capacitors are supposed to be perfect insulators. But, they aren’t. If capacitors are used in a power supply that has 80 amps, a few microamperes of leakage doesn’t show up or cause that many problems. But if a battery has to have a one-year life cycle, capacitor leakage, no matter how small, can become a major problem. Typically, the capacitors selected for ultra-low power devices have been the same ones that have been used as bypass capacitors (often tantalum capacitors). As a rule, these are not low leakage and it’s actually not a performance criterion for them.

Usually, ceramic capacitors don’t cause leakage problems but they are also not the least expensive, so they are not a default selection item for ultra-low power applications such as remote monitors. The best way to determine if the capacitors you have chosen are “leak resistant” is to read the application notes for the device. If leak resistance is not articulated, it’s best to search for a capacitor that is specifically identified as being such.

The PDS requirements for ultra-low power devices differ significantly from standard PCB implementations. These devices are characterized by small form factors, highly efficient PDS design and elimination of any potential power drain sources.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium.

About Author

About Author

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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