Risk Vs. Reward
During the recent IPC APEX expo, there was a lot of discussion about SAP, or semi-additive PCB processes. As with any new technology in PCB manufacturing, there were people that are excited to jump right in and start designing with much finer feature sizes and work through the inevitable changes to the traditional thought process. Others are in a let’s wait and see mode and of course there are a few skeptics there as well.
There were a few stand-out presentations around these ultra-high density interconnect technologies. First, Jan Pederson presented an update on the work that the IPC D-33 Ultra HDI Subcommittee has undertaken after being formed in September of 2020. As we see the convergence of new PCB manufacturing technology and substrate level technologies, these shrinking features have created gaps and conflicts with existing standards. This committee is specifically looking at things such as:
- Conductor thickness
- Thinner copper foil or deposited copper
- Plated through hole plating thickness
- Laminate defect allowances
- Performance testing coupons and requirements
- Soldermask thickness and coplanarity
Following Jan’s presentation, Mike Vinson with Averatek presented about applications of semi-additive process technology to PCB design and production. This presentation gave a very good overview of how finer feature sizes for trace and space can be utilized to reduce the number of circuit board layers and and the overall complexity of a PCB design. As a demonstration, this presentation worked through a redesign effort of an Altium reference design ultimately reducing layer count from 8 layers to 4 layers and concluded with follow on work stemming from that redesign that looked at the impact on controlled impedance with variable trace lengths and distance to neck-down the trace to route through the BGA.
This ultra-HDI PCB technology track concluded with a presentation by Clay Zha discussing the difference between traditional advanced any layer HDI technology with subtractive processes and Ultra HDI, or substate like PCB (SLP) with modified semi-additive processes for fabrication. This presentation was rooted from the perspective of a high-volume circuit board facility, one of only a handful in the world. It was enlightening learning to start to understand how a very high volume printed circuit board production facility approaches both the substrative etch any-layer technology and the mSAP technology. Much of my experience is working with high mix, low volume applications and the ability to understand this from another perspective was very educational.
I also had the opportunity to talk with the legendary Happy Holden about his journey to bring HDI to the printed circuit board market, something that he feels took 30 years to fully accomplish. Our conversation veered down the path of how we shorten this process for these ultra-high-density interconnect technologies. That conversation was eye opening. Where will the impetus for industry adoption come from?
- Will the push come from the PCB design community?
- From circuit board fabricators offering this SAP technology?
- From somewhere else?
Happy made a very good point. Marketing and sales folks, myself included, focus on the benefits of a new technology in PCB manufacturing. In the case of semi-additive PCB processes, there are many. Just to note a few of the most obvious ones:
- Miniaturization of the overall size of the printed circuit board and an electronic package. We seem to often be challenged to increase functionality while using less space.
- Reduction in overall layer count of the printed circuit board as the pinouts become much simpler to route.
- Reduction in dependence on multiple micro via layers. This simplifies the circuit board fabrication process increasing yield and reliability.
- Reduction in number of lamination cycles needed for fabrication, reducing cost and lead time for PCB fabrication.
- Improved signal integrity results with much more precise trace size and straight side walls
- Increased electronics within an existing footprint
To me, these are all excellent reasons to learn more about the technology and how to apply it to PCB design. Happy also pointed out we need to spend much more time understanding the risks, mitigating those risks and demonstrating that the rewards outweigh those risks.
How do we search out and identify risk vs. reward from both the PCB fabricators perspective and the PCB design community perspective?
We need your opinions! Let’s start a PCB design community discussion. The rewards are easy. Let’s begin digging into the unknown variables to start removing those risks. Here are few to get things started, but the PCB fabrication community is relying on us starting a robust conversation so we can start mitigating these risks and building confidence.
- What is the impact on impedance when you shrink line width and space?
- What changes to you need from a dielectric thickness perspective? Can fabricators work with thinner materials?
- What is the impact on reliability?
- What testing is being done? IST Coupons, D-Coupons, solder reflows, controlled impedance measurements?
- What materials can be used and what are the criteria for success in application?
- What are the benefits and risks to using higher aspect ratio trace (height/ width)
My challenge to those reading this blog: comment below to share your questions and we will work diligently to answer those questions!