SoC FPGA Boasts RISC-V Processor

Clive Maxfield
|  Created: December 16, 2019  |  Updated: March 16, 2020

Well, the current "hot off the press" (don’t burn your fingers") news is that the folks at Microchip Technology have just unveiled the details regarding their forthcoming PolarFire SoC FPGA family boasting a hardened real-time, Linux-capable, RISC-V-based microprocessor subsystem.

If you are "in the know," you should be jolly excited by now. On the other hand, there's so much going on these days that it's easy to let things fall through the cracks, it which case you may be asking questions like, "What's a PolarFire FPGA; what’s an SoC FPGA; and what's a RISC-V processor?" If you fall into this latter camp, don’t worry, because I've got you covered. Let's quickly skim through this one step at a time...

What's a PolarFire FPGA?

As I discussed in my column -- What Are FPGAs and Why Are They Needed? -- field-programmable gate arrays (FPGAs) are tricky little rascals, because they come in a wide variety of flavors boasting different capacities and capabilities.

The heart of any FPGA is its programmable fabric, which can be configured (programmed) to perform any digital function(s) your heart desires. In addition to the programmable fabric, FPGAs also feature banks of general-purpose inputs/outputs (GPIOs), each of which can be configured to support a different interface standard such as LVCMOS, LVDS, LVTTL, HSTL, or SSTL.

FPGAs use configuration cells to define their functionality. Some FPGAs employ SRAM-based configuration cells, which means their configuration is lost when power is removed from the system. In turn, this means that when the system is powered-up, the configuration data has to be loaded from an external source (typically an on-board flash memory device, but occasionally from an on-board processor). Other FPGAs employ flash-based configuration cells, which retain their data when power is removed from the system. In addition to being "instant on" when the system is powered-up, these flash-based configuration cells are better equipped to address concerns over cyber security threats, and they are much more resilient to high-radiation environments, being far less susceptible to radiation-induced single event upsets (SEUs).

Microchip's PolarFire devices are low-power, cost-optimized, mid-range FPGAs that employ flash-based configuration cells (these cells are actually based on SONOS non-volatile technology, but it's easier to say "flash" and then move on quickly to the next topic). The product family spans from 100K logic elements (LEs) to 500K LEs and features 12.7G transceiver cores. These devices are ideal for a wide range of applications and markets, spanning wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets.

What's an SoC FPGA?

As I noted in another column -- What the FAQ are ASICs, ASSPs, SoCs, SOMs, etc.? -- "The term System-on-Chip (SoC) refers to an ASIC or ASSP that acts as an entire subsystem. In addition to a bunch of custom functional blocks (the majority of which are typically digital, but which may include some analog and/or mixed-signal functionality), an SoC includes one or more processor cores (CPUs and/or DSPs), ancillary cores (e.g. FPUs, counters/timers), on-chip memory, and peripheral/communication cores/functions."

An SoC FPGA is a device that augments the FPGA's traditional programmable fabric with a processor subsystem, which may include things like L1/L2 cache and a floating-point unit (FPU). Communication between the processor subsystem and functions implemented in the programmable fabric is achieved using high-speed busses.

What's a RISC-V Processor?

When most people think of microprocessors, they tend to visualize things as falling into one of two camps. At one end of the spectrum we have the great big hairy processors that are used in desktop and laptop computers, like Intel's Core i9 chips, each containing up to 18 processor cores, for example. Although these little rascals are mind-bogglingly powerful, they occupy a lot of printed circuit board (PCB) real estate and guzzle humongous amounts of power.

At the other end of the spectrum we have processors that occupy less space and consume less power, and that are the mainstay of embedded systems and handheld (often battery-powered) systems. A lot of companies sell microprocessor (MPU) and microcontroller (MCU) chips; for example, Microchip Technology, NXP, and STMicroelectronics. Almost invariably, these devices are based on third-party intellectual property (IP) processor cores augmented with a unique combination of additional functions and peripherals. One of the biggest suppliers of these IP cores is ARM, which boasts an eye-watering selection of 32-bit and 64-bit microarchitectures.

The point here is that most processor IP cores are proprietary, which means you have to pay royalties to use them. By comparison, RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA). A simple overview of RISC-V is provided by the Wikipedia, which says:

Unlike other academic designs which are optimized only for simplicity of exposition, the designers state that the RISC-V instruction set is for practical computers. It is said to have features to increase computer speed, yet reduce cost and power use. These include a load-store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standards-based floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. Sign extension is said to often be on the critical timing path.

The instruction set is designed for a wide range of uses. It is variable-width and extensible so that more encoding bits can always be added. It supports three word-widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset vary slightly for the three word-widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale rack-mounted parallel computers.

If you want to know more about RISC-V, EETimes recently did a special project on this involving a bunch of related articles. One of these -- Introducing RISC-V and RISC-V Tools -- was penned by your humble narrator (links to the other articles in the special project are provided at the end of my column).

Introducing RISC-V Enabled Low-Power PolarFire SoC FPGAs

This is where we bring everything we've discussed above together. As we noted at the beginning of this column, the folks at Microchip Technology have just unveiled the details regarding their forthcoming PolarFire SoC FPGA family boasting a hardened real-time, Linux-capable, RISC-V-based microprocessor subsystem.

This announcement is exciting to me on several fronts. On the one hand, companies have built up a wealth of expertise -- and have a mountain of legacy code -- with their products and systems that are based on traditional processor offerings. On the other hand, time move on and you can't keep doing "the same old thing" forever. At some stage you come to a point where it's time to wipe the slate clean and start from the beginning. The free and open ISA of RISC-V offers just such an opportunity to start a new round of clean slate designs that are simple, stable, modular, and extensible.

RISC-V offers the ability to fine-tune low-power microarchitectures that support powerful and real-time (Meltdown/Spectre immune) operating systems for use in safety-critical systems, imaging, machine learning (ML), artificial intelligence (AI), robots, the Internet of Things (IoT), the Industrial IoT (IIoT), smart weapons, drones, unmanned aerial vehicles (UAVs), the networked battlefield, and... the list goes on.

Microchip is opening an Early Access Program (EAP) for its PolarFire RISC-V SoC FPGAs. Qualified EAP customers can start designing now with Microchip’s Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 integrated development environment (IDE) for the embedded developer. Customers can also debug their embedded applications today using Renode, which provides a virtual model of the microprocessor subsystem. If you wish to learn more, you can visit the PolarFire RISC-V SoC FPGA webpage on Microchip's website.

About Author

About Author

Clive "Max" Maxfield received his BSc in Control Engineering in 1980 from Sheffield Hallam University, England and began his career as a designer of central processing units (CPUs) for mainframe computers. Over the years, Max has designed everything from silicon chips to circuit boards and from brainwave amplifiers to steampunk Prognostication Engines (don't ask). He has also been at the forefront of Electronic Design Automation (EDA) for more than 30 years.

Well-known throughout the embedded, electronics, semiconductor, and EDA industries, Max has presented papers at numerous technical conferences around the world, including North and South America, Europe, India, China, Korea, and Taiwan. He has given keynote presentations at the PCB West conference in the USA and the FPGA Forum in Norway. He's also been invited to give guest lectures at several universities in the US and at Oslo University in Norway. In 2001, Max "shared the stage" at a conference in Hawaii with former Speaker of the House, "Newt" Gingrich.

Max is the author of a number of books, including Designus Maximus Unleashed (banned in Alabama), Bebop to the Boolean Boogie (An Unconventional Guide to Electronics), EDA: Where Electronics Begins, FPGAs: Instant Access, and How Computers Do Math.

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