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SPICE: Certainty for All Decisions
Design, validate, and verify the most advanced schematics.
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Signal Integrity
How to Design High-Speed & RF Via Transitions
High speed PCBs and RF PCBs often need to make via transitions that carry signals between layers. We’ll look at how to design these transitions in this article.
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Stepped Impedance Transformer for Complex Loads
This article will show how a complex load can be converted to a real load with an impedance transformer for any line length and impedance.
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How to Design an RF Trace Taper for Impedance Matching
Transmission line taper structures can provide superior impedance matching between two transmission lines with approximately real impedance.
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PCB Design Tips for EMI and SI Part 2
In this article, Philip tackles the basic principles and ways you should route and lay out your PCBs to minimise risks of EMI problems, and to maintain proper signal integrity.
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Reflectionless Matching vs. Conjugate Matching: An Apparent Contradiction
Are reflectionless matching and conjugate matching contradictory? When we look at the formulation for power waves and S-parameters, we see where these are different.
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PCB Design Tips for EMI and SI Part 1
Read and learn the basics of signals, energy, and fields, as well as rise and fall times in the digital domain and what this means for us as PCB designers.
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RF Signal Chain and Link Budget Basics
Learn about link budget in RF design and use our link budget calculator to evaluate your RF signal chain.
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Cutting Edge Technology in Packaging with an Interposer
In this episode, our guest Joe Dickson, tells us about the cutting-edge technology implemented in advanced packaging at Wus Printed Circuit International.
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Plated Through-Hole Vias in mmWave PCBs
Plated through-hole vias in mmWave PCBs can ruin signal integrity in your RF interconnects if not implemented properly. Learn how to size and place stitching vias in this article.
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How to Select Copper Foil for High-Frequency PCB Design
Learn how to choose the right kind of copper foil for your high frequency PCB stackup. The same ideas apply to selection of copper for high-speed PCBs.
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Why Most Via Impedance Calculators Are Inaccurate
Via impedance calculators are only useful in the low frequency range, where impedance control is typically not needed.
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The Skin Effect, Current Density, and the Electromagnetic Field
Do you know how the skin effect alters the electric and magnetic field around a transmission line? We’ll address an important misconception in this article.
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Roughness of Copper and its Effect on Signal Integrity
Bert Simonovich, a very well-known expert in the signal integrity community, is our guest in today’s podcast episode. He developed the "Cannonball-Huray" model a transmission line loss modeling, which has been adopted in several popular EDA tools.
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Should You Place Teardrops on Differential Pairs?
We’ll look at an interesting question from an OnTrack podcast guest about teardrops on differential pairs. Will they create signal integrity problems?
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A Brief Study of Stubs on a PCIe Connector
Stubs are an important topic in high-speed PCB design, and there is a longstanding guideline that stubs should always be removed from all vias on high-speed digital interconnects. While stubs are bad for high-speed lines, they do not always need to be removed. What is more important is to predict the loss profile and frequencies, and to floorplan appropriately to try and prevent such losses. In this article, I’ll look at some simulation results
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Should Ground Be Placed Below Inductors in Switching Regulators?
Should you place a ground cutout beneath the inductor in a switching regulator PCB layout? This is an important question surrounding EMI/EMC, and we’ll investigate in this article.
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Addressing Skew Sources in High Speed PCBs
Sometimes, when we talk about skew, we aren't as specific as we should be. Most discussions of skew and jitter deal with the type of skew incurred during routing, namely due to length mismatches in differential pairs and fiber weave-induced skew. In fact, there are many different sources of skew that contribute to total jitter on an interconnect, and it's important to quantify these in serial and parallel buses that require precise timing control
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