What is Carry Propagation Delay in High Speed Data Processing?

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Signal delay between logic circuits in a PCB or an IC is not something you normally need to think about until you are working with a high speed system. As data rates and capacity in PCBs continue to increase, accounting for the delay is critical to ensuring that digital data remains in sync throughout your system.

Propagation Delay Review

If you’re not familiar with propagation delay (more appropriately called transmission delay) in PCBs, I’ll explain it here. A digital signal requires a certain amount of time to move between two points in a PCB. If you’re trying to keep multiple signals in a net or in an entire system synchronized, then you need to ensure that signals arrive at various points on your board simultaneously.

Note that propagation delay in this sense refers to the transmission delay for signals traveling between two points on a PCB. This should not be confused with the definition of propagation delay that you’ll find in digital electronics textbooks.

If signals are out of sync, the bit error rate in your system can increase. When processing digital data in parallel, the signals in your net must be synchronized, thus you should match the length of all traces in your net to the length of the longest trace. Compensating skew is also critical in differential pair routing. Meandering is the best way to apply slight delays to signal lines while maintaining impedance.

Signals in different trace geometries will experience slightly different propagation delays. In you are working with an impedance controlled board, the formula for propagation delay will be relatively simple and will depend on the relative dielectric constant of the board substrate. When working the ~100 Mbps systems or higher, you’ll need to consider propagation delay throughout your board, and it is a good idea to use impedance controlled design.

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Propagation Delay and Skew in Parallel Data Processing

When processing data in parallel, additional data errors can accumulate if the propagation delay between bits is not compensated properly. Certain parallel within a net may require greater delay if the output from less significant bits determines the processing steps applied to more significant bits.

This generalized consideration may sound odd, but take the following as an example. Suppose you are designing a ripple carry adder for use in a PCB or in an IC. This device is basically a series of 1-bit adders that process input bits in parallel. The bits that make up the two digital numbers to be added must be input to each adder in parallel, and each adder may generate a carry bit.

The adder for the LSB will output a carry bit to the next greatest bit, and so on up to the MSB. The output from the LSB to the next highest bit will experience some propagation delay. You’ll also need to account for the total skew due to the rise time of the logic gates in each adder. The carry bit and the input bits in each adder need to remain in sync, and the propagation delay and accumulated skew in the carry bit require that the inputs bits in higher digits must be delayed slightly.

The total delay between each digit is equal to the propagation delay for the signal travelling between adders, plus double the rise time of the entire logic circuit in the adders (assuming both adders are from the same logic family). When you’re only working with a few bits at low speed, this will not desynchronize signals between bits. But when you’re working with, for example, 32-bit numbers at 1 Gbps or higher, the delay on the carry bit reaching the MSB will be 32 times larger than the carry propagation delay between neighboring adders.

This is a very significant delay that can desynchronize data across the adder. In order to compensate the delay on the data input to the adders for higher digits, you’ll actually need to add some delay to the input bits that reach each adder. Successively higher bits will require more delay.

The easiest way to do this is to meander traces leading into the adders for higher digits. This will compensate for the propagation delay and accumulated skew in the carry bit. Higher digits require a greater delay, but the pair of bits input to the adder must still be synchronized. The easiest way to apply this delay is to meander pairs of traces leading into each adder. Make sure to allow some extra space between pairs of traces for each adder when applying meandering.

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Note that these issues with delaying the arrival of successive bits do not just apply to adders. They really apply to any logic circuit for parallel processing where the output from processing one bit is used as an input for processing the next bit.

Components (e.g., FPGAs) that can be used for parallel processing can have a delay line structure that accumulates carry delay between successive bits. These values can reach dozens of picoseconds per bit. When you’re working with large numbers at high speed, bits in higher digits can become desynchronized from the LSB. If you are designing to specific standards that require low bit error rate, compensating delay on the input signal lines is a simple solution to prevent bit errors.

So how can you ensure data integrity in your next high speed digital system? You need routing tools that make it easy to compensate delay between elements in your PCB. The advanced routing and simulation tools in Altium Designer^® can help you avoid signal integrity problems and keep bit error rates low.

Now you can download a free trial and find out if Altium is right for you. Talk to an Altium expert today to learn more.