DDR3 Routing Guidelines and Routing Topologies

Zachariah Peterson
|  Created: January 9, 2020
DDR3 Routing Guidelines and Routing Topologies

Without volatile memory, your computer would require constant reading and writing to non-volatile memory like hard drives or Flash. Non-volatile memory is one of the things that makes modern computers so powerful and gives them the adaptability required for advanced tasks. Although DDR3 is now obsolete, DDR-based memory is here to stay and will continue to play a central role in modern computer architecture. With the right design tools, you can design to the newest generation of DDR-based memory and beyond. Come see what Altium Designer can do for you.

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Double data rate three (DDR3) is a type of dynamic random-access memory (DRAM) that succeeds earlier generations of DDR. These memories have clock speeds reaching 1066 MHz and support up to 24 GB of memory. This high clock speed and large storage capacity ensured DDR3 remained a mainstay in modern computing, but it was eventually improved to DDR4. Each new generation continues to push the limits of data rates and clock speeds in high-speed PCBs, and DDR-based memories are not likely to be replaced with a new architecture anytime soon.

With this in mind, memory designers need to make themselves aware of the various PCB design rules for DDR-based memories and how these rules are being pushed to the limits with DDR4. Designers should also stay aware of different routing topologies for PCBs as implementations of new topologies have improved the functionality of DDR-based memories, including DDR3.

Working with a great PCB design package like Altium Designer allows design engineers to implement the best routing topology for advancing the performance of DDR3, DDR4, and future memory generations. Altium Designer includes the design, interactive routing, power delivery analysis, and simulation tools you need to ensure your DDR-based designs operate at peak performance.

Routing Design Guidelines and Topology for DDR3 Routing

DDR3 uses fly-by topology for the differential clock, address, command, and control signals. DDR3 originally used T-Topology to connect memory banks to the controller, but higher performing DDR3 memories use fly-by topology to improve compatibility with highly capacitive loads and IC architectures.

Implementing the right architecture for DDR3 or DDR4, as well as placing interconnects with DDR SDRAM die packages, requires adaptable routing tools that do not constrain your topology. Signal traces are routed as differential pairs and must be precisely matched within tight tolerances compared to other computer peripheral standards like PCIe.

Signal Integrity in DDR3 and DDR4 Routing

Many of the standard design rules for ensuring signal integrity in other devices also apply to DDR3 and beyond. Higher performing memories use fly-by topology, which comes with specific requirements. Traces should be length matched to within tight tolerances, differential pairs should be tightly coupled on the same layer, and stub lengths to each memory device should be as short as possible to prevent transmission line effects and resonance in a stub. All signals within a given lane group should be routed on the same layer as this prevents propagation delay differences and skew.

In order to verify the effectiveness of your routing and layout throughout your board, you need simulation tools that directly incorporate your design data. Working within a signal integrity tool that calculates reflection waveforms and crosstalk ensures that your designs meet important performance standards on DDR3 and newer memories.

Changing view configuration settings in Altium Designer

Design layout configuration for memory devices

From DDR3 to DDR4 and Beyond: What to Expect

With DDR3 memory being obsolete and replaced with DDR4, and eventually DDR5, designers can only expect the routing requirements and topology to become more complex. Signaling speeds will increase and the routing topology for memory devices on chips will impose new layout constraints. With this in mind, you need design software that is adaptable to any routing topology while still helping you satisfy important design constraints.

Signal Integrity as Part of Design

With any new high-speed or high-frequency layout, a great simulation tool can help you diagnose potential signal integrity problems throughout your board. Potential problems can crop up at any point in your layout, and the right signal integrity tools make it easy to diagnose crosstalk, determine where termination is required, and determine how parasitics are affecting your board. You can then test potential redesigns and directly compare results during each iteration.

Signal integrity simulation results in Altium Designer

Signal integrity as part of design in Altium Designer

Altium Designer: Unifying Design and Verification Features

Given the complex demands on DDR memories, designers need programs that ease the routing and layout phase while still ensuring their design meets the basic layout standards for DDR3, DDR4, and beyond. When your design software is built on top of a rules-driven design engine, your design features will check your layout against design standards as you build your board. Your simulation tools will build models directly from your design data, and you won’t have to move your data between multiple programs.

DDR Memory Design in Altium Designer

With Altium Designer, you’ll have access to the routing, simulation, and verification tools you need to design DDR3, DDR4, and newer memory architectures that meet or beat designs standards. Only Altium Designer places these features in a single program, while other design platforms separate these features into different environments. Everything you need for DDR design can be found in Altium Designer.

Other PCB design software platforms split these important design features into different programs. With Altium Designer, you’ll have access to the best routing and topology layout features in a single platform. Altium also provides you with resources to ensure your success. You’ll have instant access to podcasts and webinars with industry experts, the AltiumLive forum, an extensive knowledge base, and design tutorials.

Instead of getting stuck with a new version of outdated design software, try working in Altium Designer’s integrated design environment. You’ll have the access to the tools you need for DDR routing and layout within and single environment. You’ll be able to stay at the forefront of DDR design when you use Altium Designer.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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