Making Multi-Channel Gate Drive ICs Adaptable

Switching power supplies rely on precise timing of MOSFETs, which are driven by PWM/PFM signals. PWM and PFM signals are generated by a gate driver, which needs to source enough voltage and current to toggle MOSFETs on in a sufficiently short amount of time. The gate drivers are designed for specific topologies or arrangements, such as a single FET driver for a flyback converter or a push-pull driver for a bridge topology.

Gate drivers are also available as multi-channel components, which will drive multiple FETs with a single device. Unfortunately, these devices have very little configurability as they are typically used for driving a group of FETs in parallel to achieve high current delivery. Making an adaptable multi-channel gate driver solution requires gate drives that can be blocked externally, such as with an FPGA or MCU.

However, with programmable mixed-signal processors, it's possible to create a multi-channel gate drive that is configurable. For example, these drives could be used in multi-phase regulators, multiple independent regulators, or a single high-power regulator with a unique topology. We will see the system topology for these types of multi-channel gate drives and the required chip capabilities in this article.

Switching Architectures with Multi-Channel Gate Drives

Multi-channel gate drives have the capability to drive the gates of multiple FETs simultaneously. These components come with multiple capabilities as a general class of components, or they may be specialized to specific architectures. For example, push-pull drivers and H-bridge drivers are a specific type of multi-channel gate drive IC but with the channel timing specialized to their respective topologies.

These components typically take in a trigger signal, enable signal, or PWM signal, and output the PWM signal necessary to toggle the gate on a FET. The exact feature used to define the required PWM signal depends on the topology being targeted. This generally means that an external microcontroller is required to generate some of the inputs, or they have to be hardwired onto the driver component.

For basic power supplies that don't require configurability or standard control, this is appropriate. For advanced power supplies and reconfigurable systems, these gate drives have limited capability that prohibits their adaptability.

Mixed-Signal Processors as Gate Drives

Mixed-signal processors are unique because they combine a digital subsection and programmable logic with an analog front end and PWM generation capabilities. This means multiple functions can be combined into a single chip along with standard gate drive capability. With a high pin count mixed-signal processor, a designer can create a multi-channel gate drive that includes a built-in serial interface and additional GPIOs or analog inputs.

The conventional multi-channel gate drive topology is shown below. When used in power supplies requiring their own control loop implementation (either analog or digital), general-purpose multi-channel gate drives will need an external controller. This controller will handle all logic and generate the PWM outputs.

There are two big downsides to this standard approach to multi-channel gate drives:

• No reconfigurability in the drive performance: the driver has the sole function of receiving PWM signals for synchronization and amplifying them to toggle external FETs
• Large GPIO count requirement: sourcing all the PWM inputs into the multi-channel gate driver requires a large number of GPIOs

A mixed-signal processor used in a gate driver topology can also be made reconfigurable with a serial interface. This is shown below.

In this system architecture, the system host sets the parameters for PWM generation for these gate drives, and the mixed-signal processor does the rest. Reconfiguration is performed over the serial interface, and additional GPIOs are available for more configuration or status signals.

Depending on the input power pin for the drive and the input power rail on the switched FETs, high-side or low-side switching may be preferable.

• High-side switching: in its simplest form, high-side switching requires a PMOS FET with pull-up to the rail voltage, and the PMOS FET toggles on when the gate voltage is low
• Low-side switching: the simplest implementation is with an NMOS as a shunt element on a load, and the NMOS turns on when the gate is high

Depending on the MOSFET arrangement, pull-up or pull-down resistors may be needed. Typically, when sourcing drive signals at logic levels and attempting to put a higher voltage into a load, we would prefer NMOS for low-side switching. High-side switching with a PMOS at logic levels may require one additional external FET to drive the gate to match the source voltage and then turn off the PMOS.

Additional Logic Processing In Mixed-Signal Processors

The advantage of a mixed-signal processor is not just the ability to customize a gate drive stage. Custom logic can be instantiated in mixed-signal processor macro cells so that unique features can be implemented. These features would typically require an additional ADC pin and/or more GPIOs on the microcontroller. But with additional GPIOs and a customizable analog front end in a mixed-signal processor, these functions can be instantiated directly without adding additional chips or using pins on a microcontroller.

With Renesas GreenPAK, designers can build a reconfigurable gate drive with additional sensing, protection, and status features thanks to built-in reprogrammable mixed-signal blocks. This brings CPLD-like custom logic and fully customizable analog circuitry into the same programmable component for advanced gate drive control.

To help designers build their custom components, Renesas provides the Go Configure Software Hub for configuring programmable logic cells, customizing the component pinout, and designing a fully-integrated analog front-end for analog signal processing.

To learn more, take a look at the GreenPAK components and reference examples.

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