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    PCB Bus Routing and Layout: The Basics

    Zachariah Peterson
    |  December 11, 2019

    SMPS circuit for a network switch

    Power supply on a network switch

    Modern computing simply wouldn’t be possible without PCB bus routing and layout. The same goes for many digital systems that manipulate data in parallel. If you’re working on a new PCB design and you need to route a bus between different devices, there are some simple rules to follow to ensure your signals aren’t distorted and that successive devices are triggered correctly. As some designers may question the wisdom of right angle turns in bus routing, I’ll address that point here as well.

    Four Rules of PCB Bus Routing

    Three important points in bus routing are designing for consistent trace impedance, proper termination, and a tight ground return path to minimize loop inductance. There is another important point to consider, which is trace length matching for parallel buses. The same issue applies to routing a clock signal alongside your bus, whether it’s a common clock or source-synchronous clock. Embedded clocks, where a clock signal is encoded in the first few bits of your bitstream, do not incur problems with clock routing in PCB bus routing.

    Using a common clock with a bus is more prone to mis-timed signalling as the number of driver/receiver ICs in series increases. This is because each IC contributes some jitter on the signal traces, and jitter adds in quadrature. Furthermore, each IC has some delay, and the clock lines from your common clock source need to be delay matched to account for the accumulated propagation delay. Suppressing jitter in the clock with a PLL is possible but not really practical, especially once we consider round-trip clocking on a bi-directional bus. As digital systems have become more complex, standardized ICs have moved to a source-synchronous or embedded clock scheme. With source-synchronous clocking, you still need to ensure that the clock is properly length matched so that the driver/receiver latches at the proper time.

    Screenshot of a schematic showing a bi-directional bus

    Bi-directional bus in a schematic

    Use of Vias in PCB Bus Routing

    One aspect of maintaining consistent signal/clock line lengths and consistent impedance is in how you route signals in your bus. Even at low data rates, you should try to minimize vias on your bus lines to prevent impedance discontinuities. If you do use vias on your bus lines, you may need to stagger your vias along the length of the trace in order to make enough room for the vias.

    This is particularly true when routing dense differential pairs with specified differential/single-ended impedance as you may have difficulty placing vias right next to each other on a group of traces. With differential pairs, you can still get away with some slight via separation as long as you arrange the vias symmetrically along the pair. You’ll have some slightly weakened coupling as you make space for your vias, but you’ll still have sufficient common-mode noise suppression at the receiver.

    PCB bus routing on a PCB layout in Altium Designer

    PCB bus routing in multiple layers

    When using low level devices (3.3 V or less) with very tight tolerances, it’s best to place power and ground planes on adjacent layers with the ground layer directly below the surface to ensure signal and power integrity. At this point, you won’t have to worry about orthogonal routing, but you will need to ensure consistent length matching and impedance for signals in your bus. This brings us to another point involved in PCB bus routing that I often see asked on EE forums. This regards the use of 45-degree or right angle turns when routing signals in a bus (or in any other situation).

    Right Angle or 45-degree Corners in PCB Bus Routing?

    We’ve talked about this issue on this blog in a recent article. The discussion applies just as much to bus routing as it does to working with a single trace. When routing a bus, you will most likely need to use right angle bends at some point. Most designers will state that you should never use right angle turns in a PCB layout due to the EMI that is created at the corner, and this would appear in a bus as well. Once a bus is broken out into individual traces, it follows logically that strong crosstalk would appear in a trace nearby the right angle corner. It is also said that a right angle bend causes the signal to reflect back towards the source.

    Mathematically, there is an impedance mismatch between the trace and free space simply due to refractive index contrast. Whenever you have an impedance mismatch, you have the potential for reflection and resonance; this is the case in any structure in which a wave propagates. However, whether the resonance can be supported as a standing wave, which would produce strong EMI and crosstalk, depends on the dimensions of the structure in comparison to the frequency of the travelling signal (either digital or analog).

    The practical reason some designers advise against right angle bends is their manufacturability. Corners can form acid traps in a PCB, where the surface tension of the etchant solution confines the etchant at the corner. This is more of a problem in tight corners, where a trace branches off at an acute angle. When etchant gets caught in an acid trap, it can cause overetching, which would increase the surface roughness of the trace. Today, this is a problem that is primarily seen with low-quality overseas manufacturers.

    Blue PCB bus routing layout

    Extremely high frequency analog signals or digital signals with very fast rise times (we’re talking sub-20 ps here!) can create a forced resonance near the corner, but only when the geometry of the right angle structure is small enough. The half-wavelength associated with the signal (use the knee frequency for digital signals) can generally be used as a benchmark for examining whether a forced resonance will arise in a given structure. In the case of a right-angle turn, the quarter wavelength should be used as you have an open structure.

    For a digital signal with 20 ps rise time (17.5 GHz knee frequency), the half-wavelength is 4.2 mm, assuming an effective dielectric constant of 4. Even if we consider a generous trace width of 0.5 mm (20 mils) to maintain 50 Ohm impedance on standard-thickness FR4, the geometry is still too small to support such a high frequency resonance, meaning any resonance will decay quickly as it radiates EMI from the trace. For practical purposes, you can effectively ignore the problems with right angle bends in PCB bus routing as any radiated EMI will be weak in most situations. With very high frequency analog signals, there is a greater potential for resonances as the width of these traces tends to be much wider.

    Check Your Datasheets and Signalling Standards!

    Although datasheets may seem to have some inconsistent information, they will generally tell you the allowed tolerances when routing a signal bus. Any length/timing mismatch and impedance variations should be entered as design rules to ensure your bus will perform as specified. Your interactive routing tools can check your board as you route, ensuring your device will work as intended.

    The interactive layout tools in Altium Designer® are ideal for PCB bus routing. These tools automatically check your layout against your design rules as you create your board. With the pre-layout and post-layout simulation tools, you can examine signal integrity in your bus design before moving to manufacturing.

    Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

    About Author

    About Author

    Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to electronics companies. Prior to working in the PCB industry, he taught at Portland State University. He conducted his Physics M.S. research on chemisorptive gas sensors and his Applied Physics Ph.D. research on random laser theory and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensing and monitoring systems, and financial analytics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written hundreds of technical blogs on PCB design for a number of companies. Zachariah currently works with other companies in the electronics industry providing design, research, and marketing services. He is a member of IEEE Photonics Society and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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