PCB Routing Angle Myths: 45-Degree Angle Vs 90-Degree Angle

Zachariah Peterson
|  Created: May 4, 2022  |  Updated: October 25, 2025
PCB Routing Angle Myths: 45-Degree Angle Vs 90-Degree Angle

One of the longest-running myths in signal integrity is the requirement to eliminate 90° turns in PCB traces. As time has gone on, the god-of-the-gaps phenomenon has taken over; the myth has gone from unfounded and has steadily been pushed off to higher frequencies. The myth is based on a complete misunderstanding of how charges and fields interact in conductors and dielectric materials, so a deeper understanding of the basic physics leads one to realize that it is totally unfounded.

In this article, I will break down the reasoning behind this myth and explain what actually happens with signal propagation into right-angle traces. We'll also look at some simulation results comparing right-angle turns, 45 degrees, and arc turns in traces to see if there is any noticeable difference. As we will see in the simulation results, there is almost no noticeable difference in the return loss of transmission lines with these three configurations, and this conclusion is supported by corresponding TDR data.

What's the Basis For the 90° PCB Traces Myth?

The myth of 90° bends in PCB traces states that 90° bends are essentially big impedance mismatches that will create strong reflections, thus ruining signal integrity. There is another version of this which states that the 90° bends will also radiate strongly, creating an EMI failure, but this is less common.

Reflections: The reason the myth persists is due to a fundamental misunderstanding of how electromagnetic waves propagate along an interconnect and how they interact with charges in the PCB trace and ground plane. The overly simplistic picture of current flow is that current is like water flowing through a pipe. I think this myth persists because many introductory engineering classes teach this picture in order to provide a simple conceptual basis for Kirchhoff's current law. The result of this incorrect conceptual picture is this idea that current hits a brick wall when it encounters a right-angle bend in a PCB trace, which implies that the 90° portion has very large impedance.

EMI: I think the EMI portion of the myth comes from viewing the region very close to the 90° bend in the trace as a partially open resonator. Following the reflection, certain frequencies in the reflected wave can constructively or destructively interfere with the incoming wave, leading to very strong fields and thus radiation at specific frequencies.

This supposition was once brought up to me several years ago by a client in the context of link tuning. The thought process was that a link tuning segment with small curvature and approximately 90° bends would form all of these resonant cavities along the length tuning region, leading to strong EMI. After a cursory look in the literature and some discussions with folks on SI lists, I was not able to find any evidence that this was true.

Effect of 90° Trace Bends on S-Parameters

To help resolve the issue, I have created a simple model in Simbeor using a standard stack-up with microstrip routing and a ground plane (4 mil dielectric, Dk = 3.35, 50 Ohm trace impedance/100 Ohm differential). S-parameters for these traces were calculated using Simbeor’s Fast SI algorithm and a full 3D Simulation for comparison. S-parameters are taken out to the 120 GHz range in order to fully investigate the range of applicable frequencies where link performance might be affected by a 90° bend.

If the myth about 90° bends in a trace is true, then we would expect the 90° trace to exhibit some or all of the following characteristics:

  • A large impedance deviation shown in a TDR plot compared to the 45° and curved traces
  • A corresponding large impedance mismatch shown in the return loss plot
  • Large dips in the insertion loss spectrum at specific frequencies or in a high-frequency range

Single-Ended Transmission Lines

First, I examined three single-ended traces: one with a right-angle turn, one with two 45 degree turns, and another with an arc turn. The three links I have simulated are shown below.

The results below show 3D Simulation results for the S-parameters, illustrating the return loss and insertion loss in three links terminated to 50 ohms referencing impedance at both ends.

It should be very clear that there is no difference in the reflection characteristics of the three traces. Note that we can only see strong reflections from the ends of the traces (near ~270 ps, equivalent to ~135 ps or the total delay of these traces).

In the return loss plots, we see that reflected power steadily increases in all cases for both the Fast SI and 3D Simulation results, and we see the different periodicities in the traces given by the peaks and valleys in the return loss plot. This is due to different lengths of the traces, which should be evident by looking at the model above.

This is supported by the TDR plot, which shows that there is a slight difference in the reflection, which is approximately 0.5% larger in the 90° trace compared to the other traces. Such a small difference in the impedance is not noticeable in the S11 plot.

The total insertion loss for each trace is shown below.

The insertion loss plot does show slight differences in the total insertion loss, but the shapes of the curves are identical and do not show any strong dips in the insertion loss which would be associated with anti-resonances in a semi-closed structure like a 90° turn in a trace. Note that the insertion loss trend from highest to lowest follows the same trend as the traces from longest to shortest; the 90° bend trace is longest and has the greatest insertion loss, while the 45° trace is shortest and has the lowest insertion loss.

Differential Transmission Lines

We can also form differential pairs out of these transmission line options, which I have shown in the image below. Note that I have not applied length-tuning because I do not want to jump down the rabbit hole of mode conversion and I prefer to only look at the issues with impedance and.

The 3D simulation results are shown below. In these simulation results, we see that the return loss profiles are very similar for all three differential pairs up to ~80 GHz. Above 80 GHz, we eventually see up to 3 dB higher return loss in the right-angle trace compared to the other two traces. We also see that the TDR plots are very similar with the 90° bend differential pair showing about a 3% impedance difference right at the right-angle bend compared to the other two traces.

While a reflection can be observed at the 90° bend in the differential pair, it is only ~3 Ohms in magnitude, equating to a 3% difference from the target impedance of 100 Ohms. This is responsible for the impedance deviation and higher return loss above ~80 GHz illustrated in the SDD11 plots.

The result that is a bit more surprising is the total insertion loss result, mostly because the myth says nothing about insertion loss. The total insertion loss curves are similar up to near 100 GHz, and we still see the differences between the total insertion loss for the various traces due to length differences. However, at 115 GHz, the right-angle differential pair exhibits a strong dip in the insertion loss. This is the type of dip you might see due to formation of an anti-resonance, such as in a stub on a via.

If we take the total insertion loss curve for the 90° differential pair, we can overlay the phase shift to determine the type of anti-resonance observed in the plot. This matches up with the return loss plot showing a strong reflection at the anti-resonant frequency.

The phase shift confirms that the anti-resonance is formed by destructive interference produced by reflection and a resulting phase shift.

Using the anti-resonant frequency in the insertion loss curve, we can calculate the wavelength corresponding to the frequency using the effective dielectric constant. The effective dielectric constant is given from the layer stack manager in the impedance tab, and this equates to a value of Dk(eff) = 2.542 for our particular layer stack. The wavelength in the PCB substrate corresponding to this frequency is 1.636 mm.

The equivalent quarter-wavelength resonant cavity corresponding to this frequency (assuming a lowest-order anti-resonance) is 16.102 mil. Given the width of the traces on the top layer being 6.96 mil with 10 mil spacing, it is tempting to conclude that the region between the traces forms a semi-closed cavity producing destructive interference at 1/8th to 1/4th of the signal wavelength. Note that more analysis would be needed, particularly a mapping of the electromagnetic field at this frequency to confirm the existence of such an anti-resonance.

Capacitance in Right-Angle PCB Traces

The results above mostly invalidate the myth surrounding right-angle PCB traces because they do not appear to show any meaningful reflection as purported by the myth. We only see some hint of excess loss in a right angle bend differential pair at 115 GHz, and this is yet to be confirmed with a more comprehensive FDTD or FDFD simulation of the electromagnetic field.

A few years ago, I discussed this with Eric Bogatin on the Altium OnTrack podcast; I asked him what is the effect of right-angle bends in PCB traces. His response was that the right-angle bend effectively adds capacitance, on the order of ~20 fF in a typical case. This is <1% of the line capacitance in a typical PCB trace, something which would produce a very small impedance deviation at the 90° bend.

Remember that the 90° bend region is also very short, causing very small input impedance deviation at the 90° bend up to very high frequencies above 100 GHz; this is consistent with what we observe above.

Watch the video below to view Eric’s remarks, or watch the entire podcast episode on Altium Academy.

 

Other Reasons to Hate Right-Angle Traces

There are some other reasons that some designers will cite to could justify avoiding right-angle traces:

  • There is a possibility that right-angle traces create acid traps where etchant gets trapped and eats away at copper, but there I have been told newer etchant additives help prevent this
  • Current density increases near sharp corners, and it is claimed that this will lead to higher EMI; I have never seen convincing evidence of this, and it is essentially a corollary of the standard right-angle traces myth discussed above
  • Due to the higher current density, electromigration is thought to occur, but experimental tests by Croes et al. (see source below) found that electromigration near right-angle PCB traces was no more severe than that from standard 45-degree traces or curved traces

My favorite reason to avoid right-angle traces is the simplest one: they produce longer routes and take up more space compared to curved or 45-degree traces.I can fit many routes in a smaller area if I use 45 degree traces versus right-angle traces, and the same goes for arc traces. In some applications, like long routes between balls/vias on a BGA or die bumps, curved traces are superior as they can contour to circular obstacles.

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Reference:

  • Croes, K., Li, Y., Lofrano, M., Wilson, C. J., and Tokei, Z. (2013). Intrinsic Study of Current Crowding and Current Density Gradient Effects on Electromigration in BEOL Copper Interconnects. In Proc. IRPS, 2C.3.1-2C.3.4.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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