On Shaky Ground—the Arguments Against Copper Pours

Kella Knack
|  Created: September 9, 2019  |  Updated: December 11, 2020

On Shaky Ground—the Arguments Against Copper Pours 

Recently on the SI-List, aka the SI Reflector, (see note at the end of this article) there’s been a spate of activity around the topic of copper ground pours and whether they are advantageous in a multilayer PCB implementation. There were arguments on both sides of the question. One person said a ground fill pour reduces EMI, another stated that it balances the copper and makes the board less likely to warp. Yet another individual claimed that it makes the board less expensive to manufacture while right next to them was someone who claimed it makes the manufacturing process more difficult. 

The ultimate result is that there are no pluses in using copper ground pours. This article will describe the history of these pours, their claimed advantages and disadvantages and why they are not valid. In addition, information on another type of fill—a signal layer fill—is provided along with its uses and benefits. 

The History of Ground Pours 

In essence, a copper ground pour refers to an area in a signal layer on a PCB that has been filled with copper. The idea of copper pours has been around in the PCB industry essentially forever and it owes its roots to EMC gurus who claimed that ground pours would reduce EMI. 

Over the years, a number of supposed advantages for copper ground pours has been put forth such as: 

  • They provide additional heat sinking. 
  • They reduce the amount of etch that needs to be done during the PCB fabrication process. 
  • They reduce the possibility that the PCB will warp. 

Lee Ritchey, Founder and President of Speeding Edge notes, “The majority of the foregoing claims are not true. It is true that copper pours reduce the amount of etch required but this is a trivial matter that does not affect the overall operation of a PCB.” 

To be fair, there are a number of disadvantages that have been noted about copper pours. They include: 

  • Patch antennas resemble a ground pour. These small areas may act as antennae and emit noise. 
  • When the copper is thick, the full perimeter heat sink makes desoldering in repair and service operations more difficult. 
  • Unless blind and buried vias are used, every via blocks potential routes and stitching makes everything more difficult. 

Ritchey continues, “Regarding patch antennas, they don’t resemble a ground pour if they aren’t over another plane and they will not function as an antenna if they are over another plane such as a Vdd or ground plane. It is true that where the copper is thick that desoldering in repair and service operations becomes more difficult but this assumes that the pour is connected to the area that you are soldering. Regarding the last point, as noted in previous articles posted by Speeding Edge, stitching vias as a whole are not useful so they should never be incorporated into a PCB design.” 

Ritchey adds, “My response to all this is that if you examine the millions of boards that are successfully made every day without copper pours, you have good reason to be suspicious. Drawing from my personal experience of being involved in the design of more than 5,000 boards, we have never done copper ground pours and none of the aforementioned problems associated with not doing them have arisen. Furthermore, none of the ‘experts’ who have weighed in on the side for ground pours have been able to present physical evidence that their claims are true. This boils down to being one of the myths that has circulated around the industry forever. Just when we think we have ‘slain the dragon’ relative to its existence, it rears its head again. This is the result of young engineers who run across these claims and are looking for input relative to their truthfulness.” 

One of the things that should be noted is that in doing the research for this article, there has been a distinction made relative to the effectiveness of copper pours on two-layer vs. multilayer boards. Specifically, the claim is that poured ground is useful on two-layer boards that lack solid reference planes and it reduces crosstalk due to capacitive coupling. 

Ritchey explains, “If you want transmission lines to not have coupling problems, they have to travel continuously over a plane. Filling in the unused space on a two-layer board with something called ground does not do that. It’s not continuous. It’s unfortunate that many people think they end up with a plane when they flood unused space with copper and call it ground. Broken patches of material that are called ‘ground’ don’t constitute a plane.” 

The foregoing information regarding two-layer boards is provided as a reference point. The recent activities associated with ground pours on the SI reflector all centered on multilayer boards. But, whether the board in question is a two-layer analog board or a multilayer digital board, the use of copper ground pours bears no significant benefits and can actually harm a board in terms of its final operation. 

Signal Layer Fills 

There are instances wherein flooding the unused space in signal layers with copper can create needed, additional plane capacitance. The fill can be Vdd if the plane next to it is ground or it can be ground if the plane next to it is Vdd. In essence, the unused space in a signal layer is flooded with copper and is then attached to the appropriate power rail, whether it be ground or Vdd, to create additional plane capacitance. This type of operation is done every day. 

As an example, Figure 1 is a PCMCIA form factor, dual-speed Ethernet adapter card. Initially, it failed EMI and was “flaky” as designed. This is the symptom associated with inadequate plane capacitance. For thickness and cost reasons, adding two additional planes was not an option. 

Figure 1. Artwork of Six-Layer PCMCIA PCB With Signal Layer Fill

This design has six signal layers. They are: L1 top side; L2, Vdd plane; L3 signal; L4 signal; L5 Ground, L6 bottom side. The unused space in the four signal layers—L1, L3, L4 and L6—have been flooded with copper. The flooded copper was attached to the appropriate power rail to turn it into plane capacitance. 

The flooding in L1 and L3 is connected to ground because the adjacent plane, L2, is Vdd. The flooding in L4 and L6 is connected to Vdd because L5 is ground. Before flooding the signal layers with copper to create additional plane capacitance, the size of the interplane capacitance was 500 pF. After flooding the signal layers, the interplane capacitance was 4000 pF or nF. The emission scans in Figure 2 show the “before” emissions in blue and the “after” emissions in red. By flooding the unused space in the signal layers of this small PCB, both the emissions and logic stability were improved enough to allow the product to operate properly. 

Figure 2. EMI Scan Before and After Signal Layer Fill for PCB in Figure 1

Ritchey notes, “There are two times when I use signal layer fill. One is when I can’t afford to add layers for the purpose of interplane capacitance. This was the case with the aforementioned PCMIA card. The other is when the dimensions of the board are so small you don’t accidentally get a lot of interplane capacitance.”


The supposed claims associated with copper ground pours have been around almost as long as boards have been designed. In truth they don’t provide any real benefit and can actually negatively affect the performance of a PCB. Another type of fill, signal layer fill, can be used to create additional interplane capacitance when board dimensions are small or when interplane capacitance isn’t already in existence.

Note—SI Reflector

The SI-List, commonly referred to as the SI Reflector, was born on May 16, 1994, with 30 members on the charter email list. It’s a forum for signal integrity engineers to post questions, answer questions, participate in the debates and listen to the industry chatter. 

To subscribe to the list go to: http://www.freelists.org/webpage/si-list. 

For access to archived postings go to: http://www.freelists.org/archive/si-list.


  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.

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About Author

About Author

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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