Interplane Capacitance and PCB Stackups

Lee Ritchey
|  Created: February 24, 2019  |  Updated: April 15, 2020

Interplane capacitance and pcb stackups cover image

This article is intended to provide guidance on the process of designing PCB stackups. It is useful to look at the evolution of technology as time has passed in order to see how the demands on the PCB stackup have changed.

In the early days of PCB fabrication, logic circuits were so slow that the only concerns were how to make connections between logic or discrete parts and provide a path for the DC power to each part. All a needed to do was provide enough signal layers for all the wires, and enough copper in the power paths to deliver the DC power with a minimum of sag or droop. It did not matter what the glass cloth used in the laminate and prepreg was, or what the resin system was, or how thick each piece of laminate was. The goal was the lowest priced PCB that would stand up to the soldering process and be reliable.

Eventually ICs became fast enough that problems such as reflections and cross talk mattered. The logic family that did this was ECL. At that time, the primary users of ECL were large computer companies such as IBM, Control Data and Cray Research. These companies had engineers on staff who did the impedance calculations needed to design stackups, and had their own in-house PCB fabrication facilities as the public market fabricators did not yet have the capabilities to exercise control of fabrication necessary to meet their requirements.

In the mid-1980s TTL, the most common logic type then in use, became fast enough that reflections became a problem requiring PCBs to have controlled impedance. Few, if any, of the engineers designing with TTL and CMOS had any understanding of how to achieve a controlled impedance PCB, so they would demand that the fabricator deliver PCBs with a known impedance, usually 50 ohms. Fabricators did not have this capability as their skill set included plating, etching lamination and drilling. Still, engineers demanded that the fabricators do the impedance calculations. The author was around during this time and spent many hours helping fabricators develop the ability to calculate impedance. Their skill at this task was very hit and miss and, in many cases, still is today.

Soon after this, crosstalk between traces running side by side became an issue requiring designers to take care on how close, side-to-side and over and under traces were routed.

By the mid-1990s, speeds had increased to such an extent that most products were failing EMI due to the need for capacitance that worked above 100 Mhz. None of the discrete capacitors placed on the power rails could solve this problem due to their mounting inductance. This gave rise to what is known as interplane capacitance or buried capacitance. Interplane capacitance is created by placing the power and ground planes very close to each other, typically, less than 3 mils.

So, now we have three demands placed on stackup design: controlled impedance, crosstalk control, and the need for interplane capacitance. Some fabricators could get the impedance right in a stackup, but there is no way for them to account for the other two. This responsibility rests with the design engineer who is the only one who knows what is needed and how to implement the required control.

By the mid-2000s, speeds of many differential pairs got so fast that the glass weave used in the laminate and prepreg could induce a phenomenon known as skew that destroyed the signal. Skew is the misalignment of the two sides of a differential pair as they arrive at the receiver. In addition, losses in the laminate began to affect these high-speed signals, forcing the engineering team to seek low loss laminates that satisfied loss goals as well as all the above requirements. A detailed discussion of materials available to satisfy all these needs is contained in Chapter 3 of this document.

For all the reasons discussed above, the design engineer must take charge of design. To do this successfully a thorough understanding of the fabrication process and materials is essential. This section will cover all the topics involved in designing of PCB stackups that meet the four constraints: controlled impedance, managing crosstalk, creating adequate interplane capacitance, and specifying the correct weave to manage skew.


Once the number of power planes, ground planes, and signal layers have been determined for a given design, arranging them in such a way that all signal integrity rules are complied with and power delivery needs are met is a series of tradeoffs. If there is a need for interplane capacitance it will be necessary to arrange the layers so that ground and voltage planes are spaced close to each other. Figure 2.1 is an example of making tradeoffs between routing layers and power plane capacitance for a ten-layer PCB. The stackup on the left side of Figure 2.1 has six signal layers, but only has one pair of planes closely spaced. This is good for routing space, but not so good for power delivery if there is a need for interplane capacitance. The stackup on the right has only four routing layers (the two outer layers are too far from the nearest plane to achieve the proper impedance), but it now has two sets of plane pairs. This is good for interplane capacitance, but not as good for routing space.

Figure 2.1 Two Possible Ways to Arrange the Layers in a Ten Layer PCB.

In both cases above, all the signal layers are mated with planes across pieces of laminate except the two outer layers. As mentioned earlier, these layers will be too far from the nearest plane to achieve the proper impedance. They can be used for power traces and component mounting pads.

Once the arrangement of layers has been determined, the next step is to select the thickness of each dielectric layer to achieve the best performance at the lowest cost. To minimize crosstalk, it is advisable to select the thinnest laminate that meets SI goals for the space between signal layers and their plane partners. Once this is done, the trace width needed to achieve the target impedance is calculated. Following this, the thickness of the prepreg between the power planes is selected to satisfy the breakdown voltage requirements, and allow enough resin to fill the voids in the adjacent planes. This will usually be a single glass ply that begins three mils thick and presses down to about 2.5 mils.

In the example on the right in Figure 2.1, there are three prepreg layers that remain to be chosen. These are the one in the center of the stackup and the two just below the outer layers. (The outer layers in this stackup are not usable as controlled impedance layers, so their height above their underlying planes is not critical.) The thickness of all three of these spaces can be used to add material in order to arrive at the final thickness desired as changes in thickness in these three areas have little effect on the overall performance of the PCB.


As the speeds of signals continue to increase, the demands placed on the PCB become more complex. Some of those demands, as mentioned above are controlled impedance, controlled crosstalk, interplane capacitance, managing path loss, and glass weave style control.

For these reasons, the documentation required has become more complex as well. The stackup drawing must contain more information than in the past, and the fabrication notes will need to be expanded. Figure 2.2 is an example of the amount of information that must be included in the stackup drawing to ensure the PCB is correctly fabricated. Notice that there is no impedance information on the stackup drawing. The reason for this is that all the other requirements must also be met. Therefore, the stackup drawing specifies the overall cross-section of the PCB that meets all the SI goals. The design engineer must determine all of these including impedance and specify the total cross section.

Figure 2.2 A Stackup Drawing with Adequate Information



As mentioned earlier, there are a number of calculations that must be made to arrive at a final stackup drawing and the routing rules for a design. Among these are;

  • Impedance

  • Cross talk spacing

  • Interplane Capacitance required

  • Allowable trace loss

  • Allowable skew


The most accurate method for calculating impedance is with a tool that uses Maxwell’s equations. The least reliable method is to use any of the equations that were once the only choice. There are a number of products on the market that use Maxwell’s equations in a 2D field solver. Any of these produce accurate answers provided the correct dielectric constants are used. The correct dielectric constant for each type of laminate is obtained from the laminate manufacturer’s laminate information. Table 2.1 is a typical laminate information sheet with dielectric constant (er or Dk) as a function of frequency. Notice that the Dk varies with both resin content and frequency. It is imperative that the correct value is used when calculating impedance. Unfortunately, the author has discovered that many fabricators do not use the correct Dk values when calculating impedance, resulting in PCBs that are fabricated with the wrong impedance.

Information courtesy of Isola

Table 2.1 A Typical Laminate Information Table

Impedance calculating tools commonly available in the PCB industry include:

  • Polar Instruments SI8000 and SI9000

  • Mentor Graphics Hyperlynx

  • Z-ZERO

  • Cadence

  • HFSS

  • ADS

All these tools produce accurate impedances and are comparable in accuracy. Polar SI8000 is the most commonly used tool at fabricators.

A new alternative is available since the release of Altium Designer® 19, the Stackup Manager uses Simbeor SFS solver for accurate impedance calculations with the validated and verifiable accuracy. See it in action: 

See more on the accuracy of the impedance and losses at app note 2018_05 here.


Crosstalk is the unwanted interaction between two traces that are spaced too close together. The stackups in Figure 2.1 have pairs of signal layers one over the top of the other. If a signal in one of those layers lies over the top of one in the other layer, the crosstalk will grow so rapidly that no amount of overlay at the speeds of current technology can be permitted without causing a crosstalk problem. The only safe routing strategy in this case, is to route one layer in the X direction and the other in the Y direction.

When traces run side-by-side in the same layer, care must be taken to make sure the spacing between traces and the height of the nearest plane is such that crosstalk goals are met. The only way to arrive at reliable spacing rules is to employ one of the simulation tools meant for the purpose. Rules such as 2H or 3H are arbitrary and unsafe to use.


Interplane capacitance, the capacitance formed by two planes closely spaced to each other, has proved necessary to provide the very rapid switching currents needed by modern logic to drive transmission lines and supply current to IC cores. Failure to include enough interplane capacitance in a design is the most common source of EMI failures.

Determining the amount of interplane capacitance needed is accomplished by employing one of the analytical tools designed for this purpose. The PCB stackup design cannot be completed without performing this analysis.



As the speeds of data links continue to rise, the potential for signal degradation due to losses along the length of the signal paths, from losses in the dielectrics and copper can become significant. Deciding whether the loss in a proposed path is acceptable based on trace width and the loss properties of the dielectric is a complex analysis that requires a tool such as ADS, HFSS, Hyperlynx Gigahertz or similar tool.

There are a number of laminates on the market that have been engineered for very low loss. Deciding when a design needs one of these depends on four things. These are:

  • Length of the signal path

  • Frequency content of this signal

  • Ability of the transmitter/receiver pair to compensate for loss

  • Roughness of the copper in the planes and on the traces

Trace width is not on this list because it has been shown that for the allowable trace widths in most designs, changing trace width to reduce loss (making traces wider), is not a useful method for reducing loss.


Skew is the misalignment in time of the two signals in a differential pair as they arrive at the receiver. The primary source of unwanted skew is differences in travel time on each trace due to the uneven way in which the fibers in the glass weave are spaced. As the speeds of differential pair links continue to increase, the effect of an incorrect weave can cause a design to fail due to excess skew. 

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium or access one of our handy solution pages for help with your layer stackup in PCB design.

About Author

About Author

Lee Ritchey is considered to be one of the industry’s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge, an engineering consulting and training company. He conducts on-site private training courses for high technology companies and also teaches courses through Speeding Edge and its partner companies. In addition, Lee provides consulting services to top manufacturers of many different types of technology products including Internet, server, video display and camera tracking/scanning products. He is currently involved in characterizing materials for ultra high speed data links used throughout the Internet.
Prior to founding Speeding Edge, Ritchey held a number of hardware engineering management positions including Program Manager for 3Com Corporation in Santa Clara and Engineering Manager for Maxtor. Previously, he was co-founder and vice president of engineering and marketing for Shared Resources, a design services company specializing in the design of high-end supercomputer, workstation and imaging products. Earlier in his career, he designed RF and microwave components for the NASA Apollo space program and other space platforms. Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 2004, Ritchey contributed a column, “PCB Perspectives” which appeared on a monthly basis in the industry-renowned trade publication, EE Times.

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