SIG/GND/SIG + PWR/GND Stackups: Will This Work in 4-Layer PCBs?

Zachariah Peterson
|  Created: October 17, 2023  |  Updated: March 8, 2024

I've had multiple people ask me about a particular kind of 4-layer PCB stackup which uses a dedicated layer for power. No, it is not the SIG/GND/PWR/SIG stackup, of which I am in favor of in specific types of power systems. This stackup is the SIG/GND/PWR/GND stack up, which is a kind of stackup I have not contemplated in the past.

Sure, it is very similar to the SIG/GND/PWR/SIG stackup in that we have a dedicated layer for power, and the bottom layer is dedicated to GND. The main justification is for shielding; if you place signals on the same layer as power, then the internal signals will have significant shielding. But when you break down why this might be used, you might be wondering if you are using up too much space for dedicated power rails on their own layer.

What other challenges might arise from the use of this type of stackup? In this article, I'll break down why you might want to use or lose this type of 4-layer PCB stackup for your design.

Dedicated Power Layer?

I think the first thing to do is to think about your engineering requirements and ask yourself this question:

  • Do you really need a single layer for power?

Like most things in PCB design, you'll see a lot of debate about this. The Bogatins of the world will usually say “no,” and I seem to recall personally hearing Rick Hartley reject the use of a power plane in a four-layer stack up. I think both answers carry unspoken context, and I see reasons to give power its own dedicated layer:

  • You have multiple power rails that need to carry a lot of current.
  • You want a convenient way to bring power to anywhere on your component layers

The first point is not a corner case, it is actually quite common. Many digital processors and ASICs might need different voltages or different rails which are isolated from each other, demanding the use of separate regulator circuits and separate rails. The second point is more a matter of convenience; if you have extra space on a layer to fill in with copper, why not use it for power?

Once you can answer the above questions, you can look at how to use the top half and the bottom half of the layer stacks for your PCB layout. Let's look at each half of the stack up and we can see why this kind of stackup might be valuable for your PCB.

Top Half - SIG & GND

One of the major reasons you would use a 4-layer PCB is to provide a ground plane very close to your components/signal layer, primarily to support digital signals. The nearby ground improves nearly every aspect of signal integrity and EMI/EMC. We can see this by looking at a typical example for any digital PCB.

The main reason to do this is to provide the ground reference required for digital components clustered on the top layer, such as in the PCB example shown below. This board contains many digital circuits and power circuits, and both of these circuits benefit from the ground plane on L2. This project is a USB hub, so it includes multiple differential pairs which need ground to provide reasonably small trace widths. For the power circuits, nearby ground provides EMI suppression from switching regulators.

This USB hub uses SIG/GND as the outer layer pair to provide easy differential pair design for the USB lanes. Design submitted by Hany Hamza.

Bottom Half - PWR+SIG & GND

Assuming the top half is only being used for signal, the bottom half in the SIG/GND/PWR/GND stackup would only be used for power. The power layer can be divided up into multiple rails with different voltages, or it can be used as a complete plane at a single voltage. The former is a typical approach in some digital systems in order to support many isolated rails in some processors and ASICs.

This 4-layer PCB stackup defines L3 as a signal layer, but it is being used as a power layer with multiple rails. Design submitted by Kombo Chiganze.

If you don’t have multiple voltages, there is nothing wrong filling in with copper, it will be quite easy to reach power pins on components without needing to route traces in the component layer.

I like to bring up the point that it is okay to do this even if you are not operating at high current. Consider the calculation results from an IPC-2221 calculator or IPC-2152 calculator; the currents that large rails can handle could be quite high, but that doesn’t mean you cannot use large rails when currents are low.

Here is a summary of how to use copper regions for different power requirements.

High currents at a single voltage

  • Use a single rail for power, use SIG/GND/PWR/SIG if additional trace routing area is required

High currents, multiple voltages

  • Use multiple rails in the power layer

Low currents, single or multiple voltages

  • Multiple voltages: Use small rails, use extra space for traces
  • Single voltage: Route traces and fill in with copper for power, enforce clearance

In all of these instances, you could provide additional space in your power layer for signal traces. The ground layer on L4 will help shield these signals, which will make the design attractive for analog signals. Be careful with this as any noise in the power layer can couple into inner signals, so low-level analog signals might be in danger of receiving noise from noisy power rails.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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