Recently, when browsing through a major electronics industry blog, I came across a 10 top ‘design for manufacturing’ mistakes article. I read the article thinking it could be interesting and inventive, but to my surprise, it was essentially a copy-and-paste of an article I had read 10 years ago, which itself was a rehash of an article almost 10 years older. I’m not a fan of reworking old articles and labeling them as ‘new’ content, as it’s a prime way of creating and perpetuating false rules of thumb or worse, invalid ‘industry best practices’. The electronics industry changes so rapidly that most content written over a decade ago is now obsolete. Let’s take a look at a few of the top mistakes these articles mentioned and shed light on them, then consider some actual top tips that are relevant to today’s industry standards.
It’s now the second half of 2019; we are in an age where even the cheapest, most trivial prototype PCBs get a flying probe check to discard boards that have any electrical faults, even if the issue was with the etch process. The top mistake an older article I read warned us to avoid was acute angles, because they can create acid traps. If you are using a toner transfer and home etching, this might be true, but with modern manufacturing methods, this isn’t going to be an issue.
Photoactivated etching solutions used on boards with photoactivated resist layers are very common in board fabs. These etchants give crisp sharp features, and if the etchant pools, it won’t get enough light to activate. You can even use photoactivated resist layers at home very easily. Contemporary etching processes make acid traps much less of a risk than they ever were in the past.
I generally agree with via-in-pad being a mistake. However, the article used an example in which the via-in-pad should indeed have been used for thermal reasons. Many high current devices require via-in-pad to the extent that the manufacturer recommends it for the footprint. It's the only way you will be able to get the heat off the package efficiently enough.
The article claimed that if you use a via-in-pad, it will wick away all the solder and leave you with a dry joint. This is 100% true; capillary action will indeed pull solder through, however, tenting the via on both sides will prevent that completely. In specific cases, if you really don’t want any solder mask on your pad, you can tent just the opposite side of the via to the pad. This works for vias up to 0.4mm quite reliably, but if you’re still hesitant, you can add some silkscreen to the via on the opposite side as well, thus ensuring the via is fully capped.
Incidentally, it’s not just vias on the pad you’ll need to be careful with. If you put a via that has not been tented very close to a pad, it may also suck solder away from your pad.
The article argued that if your manufacturer is going to work with incredibly tight tolerances, using a multitude of similar, yet not exactly identical hole sizes on your board might increase your board cost. However, a look at today’s drilling technology shows that this is far from truth. Tool magazines in industrial PCB drills contain pretty much every micro drill size known to mankind, and tool changes are incredibly rapid. Even if all the 13.5mil and 14mil holes are drilled by their exact size drill bits, it may only take an extra second or two per PCB sheet. Generally, the board fab will just round all of these holes to one size as long as the sizing fits within their tolerance requirements or within tolerances you specified on a drawing.
The same goes for slots in a PCB. I haven’t found a PCB fab that will penalize me for using very small slots (30-40mil) or specify a separate milling route for squaring up corners from a larger tool on a slot with a 20mil end mill.
Avoiding silkscreen from a component getting on the pad of another can be impossible for a tightly routed board. In my Altium library, I use both a pin 1 designator silkscreen dot and a silkscreen feature under the component where possible to make orientation easy to figure out for this exact reason. I have yet to find a budget or expensive board house that won’t automatically clean silkscreen off pads for you, or at least ask if you want them to.
If you received a board with silkscreen on a pad, it could certainly cause major issues with solder wet-out on that pad, which would cause a bad joint. With today’s manufacturers, however, it’s not an issue I’ve experienced.
This ‘mistake’ just makes me shake my head in wonder. How can you forget to add mask between the pads on a board? Altium and pretty much every other design tool will take care of this for you. Many fine pitch components have clearance gaps between pads that don’t allow any solder mask between pads. Nevertheless, I’ve seen Altium generate mask between pads that is 1/1000 of a mil wide. Even the default design rules in Altium work perfectly for specifying solder mask between pads.
If the mask between the pads is too small, a good board house will let you know before proceeding, and a less concerned board house will just delete the feature and carry on.
For years now, I’ve been publishing a large open source database library of components that allows you to place real world, purchasable parts into your design at the schematic capture level. With complete and accurate 3D models, and Altium’s 3D view of the board as well as collision checking on 3D bodies, it's very difficult to complete a design where parts collide. You can now get the same functionality across a broader range of components using Concord Pro, an add-on product for Altium.
Its been at least 5 years since I’ve last been capable of erroneously specifying a part in my bill of materials which won’t fit the footprint I placed on the board. I’ll relegate this ‘mistake’ to not using the best tools during design, rather than being a mistake with the design process itself.
Now that we’ve ruled out a wide range of ‘top mistakes’ from years gone by, let's look at some tips that might help you if you’re just getting started with designing for manufacturing.
It’s very easy to place a mechanical hole for a fastener and forget to take into account how big the head of that fastener might be. Something that is bigger, yet ironically easier to forget, is the washer for that fastener. I generally place a via with the correct clearance hole for the fastener and specify the annulus (the copper circle attached to it) to be the same size as the largest washer available for that fastener (where multiple washer standards exist), plus a little bit extra. If you really need to run a trace under the head of the fastener and you just can’t do it any other way, add a solid silkscreen over the fastener area as extra protection for your trace. The small amount of extra protection the silkscreen provides could be what saves your trace from damage when someone over-tightens the fastener.
To be double sure, add a 3D model of the fastener to your board and mount it in the hole. This will ensure you can get the fastener in and out, and you don’t go placing the body of another component in the way.
Altium pretty much takes care of this one for you. However, if you’ve bypassed the default settings to sneak a trace in, make sure it’s not too close to the edge. A lot of articles online will mention corrosion as the undeniable impediment when optimizing copper clearance, because you don’t want exposed and unplated copper. When running a fine trace close to the edge of the board, however, the end mill/slot drill might chip the trace and destroy it. When using V-Scoring to separate boards in a panel the score takes up a certain width and is not always perfectly accurate, which can easily damage or remove the trace too.
After putting slots in the board, I usually do a final check to try and find errors with clearance before I submit my work.There have been times I mistakenly went and ran a trace on an internal layer right across a slot. In your board preferences, set the milling layer to the layer in which you have your milling paths so Altium will render the slots in 3D view. After that, copy the milling layer over to your keep-out layer to ensure design rules will highlight any existing issues, and prevent any future ones.
Altium has design rules for solder mask expansion on vias which can be used for tenting, so make use of them. Anything under 15mil/0.4mm should be tented. Above that, you may want to consider how thick the solder mask from your board fab is. A fully tented and closed off via is a good thing, as it prevents any corrosive material such as flux, dirt, and moisture getting into the hole and corroding your via.
When the hole gets too large to fully cover, attempting to tent it might instead create a mostly covered hole that more easily traps the things you’re trying to keep out. In such circumstances, you’re better off using untented vias and allowing the plating to protect the hole. Keep your solder mask clearance around the hole quite small though, as you don’t want the via to become a potential location for a short.
Very high spec boards will likely have the vias filled with epoxy during manufacturing. If you’re designing those, the tips we covered are probably not relevant to you as you are long past needing any design for manufacturing tips!
A lot of products I design use double-sided boards. However, you should have a good reason to go double-sided. If you are tempted to put just one or two passives on the bottom of the board, you could be causing yourself a lot of pain when you get to assembly. Either fully commit to a double-sided design or stay single-sided. If you don’t have a really good reason to put parts on both sides of the boards, just stick with the top layer. If size constraints or board density specifications require a significant quantity of components to go on the bottom, then so be it.
You may also consider using a smaller package component to claw back some board real estate. For most assemblers, an 0402 component is undemanding and will be far cheaper than placing components on both sides of the board. Many assemblers will not have significant extra costs or waste when using 0201 passives, which can give you a huge amount of free space even if you’re using 0402 parts already. Check with your assembler before using 0201 or smaller, since older machines may be unable to handle them reliably. If the assembler can handle smaller components, it's likely to be much cheaper than relying on double-sided assembly.
Finally, and I hope this goes without saying, make sure all your output files are there. I’ve been through situations where I forgot to add NC drill files to an output job file, or accidentally deselected one layer too many for the gerbers. Use a gerber viewer, even if just the one built into Altium, to check that all your polygons are fully rendered, all your drills are in place, and silkscreen and mask are present where needed. If you’re sending the board to an assembler or a contract manufacturer, make sure you have the paste layer(s), pick and place centers, and assembly drawings exported as well.
I have to admit, thermals are a bit of a pet peeve of mine. Some software defaults to adding thermals on pretty much everything. If you add a via, it gets a thermal; add a pad, it gets a thermal. Thermals can create points of high inductance and start causing issues with moderate and high-speed signals. In high current situations, the thermal’s low copper cross section may not be able to conduct enough current.
Thermals can make hand soldering easier in large copper pours, and may have been required for older wave soldering machines. If you are designing a primarily surface mount board with a couple of through-hole parts such as connectors, there are not many use cases for a thermal on a pad. The surface mount parts will undergo reflow soldering, meanwhile the through-hole parts will be soldered with a selective solder machine.
This ability to prevent heat transfer from the pad over to a large copper pour goes both ways. On one hand, it may make assembly a fraction easier, but on the other, it will equally prevent any heat from escaping a package. I’ve seen multiple production boards with a D-Pak (TO-252) or a similar package that had thermals on the ground pad, which fully butchers the ability of the package to dissipate heat.
Current density on high amp package with thermals enabled. Imagine the thermal issues.
Likewise, thermals on vias will severely limit how much current and heat they can transfer. Even worse, clustering vias together for extra heat or current transfer can starve the area of any copper and decimate current or heat carrying capacity in the entire region.
If you are designing boards for modern fabrication and assembly processes, you can add features that would not have been reliable a decade or two ago. The volume and complexity of boards over the past 2 decades have risen exponentially. To allow this pace of change, PCB fabricators have been using more efficient, more accurate and more effective methods to create boards for highly sophisticated designs. Post fabrication electrical testing is standard even in the lowest budget fabrication facilities, and catches the vast majority of production issues. If you are designing a high current board using a power distribution analysis tool such as PDN Analyzer from Altium, can assist with catching mistakes regarding insufficient copper area for the application. If your design is not robust enough to handle the current, frequency, or thermal requirements of the application, it doesn’t matter if the board is electrically functional or not.
Have more questions? Call an expert at Altium.