Validation Structures for Signal Integrity

Jason J. Ellison
|  August 20, 2019

Let’s say you’ve just received a populated switch or GPU PCB from your favorite PCB fabrication and assembly site. You sit down at your computer and start up your GUI or console to begin transmitting data. Trouble begins—the protocol to bring up the link isn’t working. What do you do? Checking the voltages and jumper positions is easy enough, but what about the signal integrity of your channel? Assuming that you did all of the required simulations before fabrication, you probably want some way to validate the design performs as predicted. You can only do that if you have added the right structures to the PCB! 

In this article, I describe several structures to place on your board for SI design verification and how to use them.

If you can only have one …

You always want to check if your brand new printed circuit board does what it was intended to do. In terms of SI, you want to check if your traces have the correct loss and impedance. Both can be checked with one structure: the 2x-thru. 

The 2x-thru is a transmission line two times length x, where x is usually a length of a thru transmission line on your PCB. Hence the name 2x-thru. You want to pick x in such a way that it’s relatively easy to place on the board. Meaning, you don’t want it to take up much space. On PCBs designed to test a single component, x is the length of the trace from your coaxial connector to the device under test. If your PCB is a functional device, you may want x to be the same length as your longest transmission line. That makes sense if you’re testing a short trace from an I/O port to a SERDES on an HCA. However for designs with longer traces, like an Ethernet switch, you may want x to be half the length of your trace from an I/O port to your SERDES. 

You need to have an idea of what you expected from the PCB before you check it. This is, in fact, Eric Bogatin’s rule of thumb #9, and, in my opinion, one of his most impactful rules for your day-to-day life as an engineer. To get an idea of how much loss to expect, you can model your traces with a closed form equation or with a 3D EM solver. Personally, I find closed form equations work best for loss. Impedance is a little more complicated to anticipate since the PCB fabrication site’s process influences the results. A common practice is to assign your high-speed digital traces a target impedance and a tolerance. Most board houses can hold +/- 10% and some can go down as low as 5%. Tighter tolerances come at a premium cost.   

Checking loss and impedance is fairly straightforward. To check loss, use a VNA or a TD-VNA. Both do a great job of measuring loss accurately. You just want to be sure you have a valid calibration before you measure. To check impedance, use the reflection S-parameters that come with the above measurement and convert them into the time-domain. Impedance can also be measured directly with a TDR. I personally recommend using a VNA (figure 1) or TD-VNA (figures 2 and 3). Impedance rises with time. This is a physical phenomenon caused by the frequency dependant impedance of the transmission line. Since impedance is not a straight line, what point do you pick? Many SI engineers pick the point in the middle; don’t do that. The best point is the first stable point on the transmission line (figure 4). That yields the most accurate answer. If your impedance is outside of the range you specified on the print or drill drawing layer, you can ask for a new board or a refund. Doing this can impact your relationship with the fabrication site. So, I recommend being careful before making that request.

Figure 1. ZNB20 VNA from Rohde & Schwarz® showing a setup to verify the high-speed differential 2x-thru on a PCB with probes. Image courtesy of Rohde & Schwarz® 

Figure 2. A TD-VNA from Multilane inc. Part number ML-4035-TDR. Image courtesy of Multilane inc. 

Figure 3. TD-VNA from Teledyne LeCroy measuring an edge-card channel. Image courtesy of Teledyne Lecroy.

Figure 4. Impedance profile from simulated S-parameters of a 10 in transmission line.

Once you have the S-parameters of your 2x-thru, determine the loss by the length and you have a very reasonable estimate of loss per meter. You can then scale that result to all the trace lengths on your board. In most cases, you’ll find the board has more loss than expected. This is, of course, not what you want to hear. The source of this extra loss is almost always surface roughness. Many SI engineers claim surface roughness is a predictable phenomenon, and to some extent, they are right. There are algorithms which adequately predict its ill effects, but the algorithms are all really a fudge-factor tacked onto conductor losses. From what I can tell, the snow-ball algorithm is the closest thing to a first-principles explanation of surface roughness. Even that doesn’t predict all of its effects, namely, it doesn’t predict phase discrepancy, and that means it’s incomplete. My point in saying all this is that you can’t really predict the effects of surface roughness perfectly unless it is not there, and that is why we as SI engineers often mispredict IL performance. 

If you can spare some extra space …

The Beatty standard (figure 5) is the next structure to consider placing on your board. The Beatty standard is a serial resonator created by tripling the width of your 2x-thru trace for a certain length. The resonant behavior is determined by the following equation.

Figure 5. A micro-strip Beatty standard.

Where F is the frequency in GHz, c is the speed of light, l is the length of the Beatty standard, and εr is the relative dielectric constant of the material. If you are using a microstrip structure, εr is the effective dielectric value.

Peaks are observed when n is odd, and nulls are observed when n is even. For example, see the plot below that uses the following inputs:

Figure 6. Example Beatty standard modeled with QUCS.

You need to de-embed the coaxial connector and a portion of the trace to observe these peaks and nulls. De-embedding is the process of mathematically removing the electrical effects of a test fixture from measurement. To de-embed the fixture from the Beatty standard measurement, use a process called 2x-thru de-embedding. 2x-thru de-embedding is where a 2x-thru is used to create fixture models that are removed from the fixture using matrix algebra. I show an example of de-embedding a fixture from a Beatty standard measurement on the SI Journal and have it below for reference [1]. This article also has more information about de-embedding in general.

De-embedding can be quite complicated. However, free tools are available. If you use MATLAB or Octave, you can use the de-embedding functions on Gitlab [2]. I personally champion this code. So if you have questions, please contact me directly:

It is important that several peaks and nulls are in your observable frequency band so design the length of your Beatty standard around the VNA you have. Here is a table for some good lengths to use based on a VNA’s maximum frequency.

Table 1. Design criteria for a Beatty standard based on VNA maximum frequency.

VNA Maximum Frequency

Length of a microstrip Beatty Standard

Length of a stripline Beatty Standard

26.5 GHz



50 GHz



110 GHz



These values ensure there are 10 peaks and nulls available across the entire bandwidth of the VNA. 

Now, what to do with the Beatty. First, you can validate your PCB DK. The Beatty standard length is known, so you can model the structure with your expected PCB materials. If the delay of the beatty is incorrect, adjust the DK to correct the discrepancy. This will also make your peaks and valleys line up in the frequency domain. Once that is complete, you can determine the trace width by adjusting it in your model until the measured and modeled impedances match. In some designs, knowing the width of the traces helps understand where extra crosstalk is coming from. I learned of this process from an article by Heidi Barns and Jose Morarea [3]. There is also another interesting read on Beatty standards by Chun-Ting Wang Lee. It was first presented at DesignCon and is now available on the SI Journal [4].

Now, you have determined with fairly high confidence how your design is performing electrically and how the artwork compares to what is fabricated. Seems like you have enough information now, right? Well, you can still take it one step further. 

Bonus Structures

The last structure to consider is a 1X or 3X-thru. By de-embedding the 1X from the 2X-thru, or the 2X-thru from the 3X-thru, you are left with an isolated transmission line with 1X length. This yields higher accuracy for loss scaling than the 2x-thru alone and gives access to more algorithms for dielectric material property extraction. For example, [5] shows an algorithm for extracting the effective surface roughness and the DF quite accurately. If you are interested in experimenting with SI related measurement algorithms, you can also use this structure to write your own TRL code using the two lines of different lengths. 

If you are not concerned about the PCB material or creating de-embedding code, you can also add a suspicious feature of the PCB as a DUT. For example, via transitions can be very problematic, especially if you hired a contract manufacturer to do your design for you. To test a suspicious via transition and perhaps your contract manufacturer’s SI mettle, you can add a via with some surrounding trace as your DUT. In that scenario, you have 1x of trace length, your suspicious trace and via structure, and another 1x of trace. By de-embedding the trace from the measurement, you isolate the via to understand if it will present SI problems in your link.

Altium Designer® offers excellent signal integrity tools for PCB designers. Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium. 


[1] Jason Ellison, “Test Fixture De-embedding 101,”, Signal Integrity journal, June 2017

[2] IEEE P370 Open-Source Code,

[3] H. Barnes, “Analysis of Test Coupon Structures for the Extraction of High-Frequency PCB Material Properties”, SPI, pp 1 – 4, May 2013

[4] Chun-Ting Wang Lee, “ Resonant Test Structures: Primer and Signal Integrity Applications,”, Signal Integrity Journal, Sept 2016

[5] J. J. Ellison, “A Method of Extracting the Effective Copper Surface Roughness of a PCB Laminate In Situ,” IEEE Transactions on Electromagnetic Compatibility, Volume: 60, Issue: 4, Aug. 2018

About Author

About Author

Jason J Ellison received his Masters of Science in Electrical Engineering from Penn State University in December 2017.
He is employed as a signal integrity engineer and develops high-speed interconnects, lab automation technology, and calibration technology. His interests are signal integrity, power integrity and embedded system design. He also writes technical publications for journals such as “The Signal Integrity Journal”.
Mr. Ellison is an active IEEE member and a DesignCon technical program committee member.

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