PCB Ringing: What Causes and How to Reduce Ringing In Circuit Boards

In any engineering discipline, there are some terms which are thrown around and can have multiple meanings. In PCB design, one of those is the word ringing. The term refers to underdamped oscillations observed in an oscilloscope or in time domain simulations of signal dynamics. Rather than referring to a specific signal integrity problem, ringing can be observed in many circuits, but it tends to arise most often in poorly decoupled digital circuits and in AC power integrity.

To give a full view on what is ringing in a PCB, we will discuss common areas where it arises and can be easily observed. Ringing is just a simple oscilloscope measurement away and often has simple solutions, depending where it arises.

A Basic Ringing Measurement in a PCB

Ringing can be observed in multiple cases, such as in DC power, square wave signals in general, and superimposed on digital data. Ringing can be measured with an oscilloscope, and the scope bandwidth must be chosen based on the rise time rules relating to the Gibbs phenomenon. An accurate measurement can capture a high frequency oscillation, typically in the high kHz or MHz range. An expected waveform is shown below.

From this view on an oscilloscope, the ringing frequency can be measured. In some design contexts, this tells you something about the operation of the circuit or what needs to be done to eliminate the ringing. Sometimes, this is as simple as adjusting the resonant frequency, adding a clamp circuit, or adding damping to the circuit. The exact solution depends on the system you're looking at, and some common instances from signal and power integrity are listed below.

Isolated DC/DC Converters

In isolated DC/DC converters, ringing arises from the interaction between parasitic inductance in the transformer windings and the output capacitance of the driving MOSFETs. Every time a MOSFET switches off, the energy stored in the transformer leakage inductance has no immediate path to discharge, and it resonates with the drain-to-source capacitance of the FET. The result is a high frequency oscillation superimposed on the drain voltage waveform, often reaching amplitudes well above the nominal bus voltage.

For example, in a push-pull topology, two MOSFETs alternately drive opposite ends of a center-tapped primary. When one FET turns off, the leakage inductance of its half-winding resonates with the FET's body capacitance, producing voltage spikes on the drain node. In full-bridge and half-bridge topologies, the same mechanism occurs at each switching transition, but the interaction is distributed across four or two switches respectively, and the transformer magnetizing inductance can participate in the resonance if the dead time is not well-controlled.

RCD clamps in a push-pull topology. Each FET needs a clamp circuit to dampen the ringing observed on the drain of each FET.

The ringing frequency is set by the resonant tank formed by the leakage inductance and the MOSFET output capacitance, typically landing in the tens of MHz range. Left unclamped, these oscillations stress the FET beyond its voltage rating and radiate EMI through the switching loop. The standard mitigation is an RCD or RC snubber clamp across the MOSFET or across the transformer winding, tuned to damp the resonance without excessive power dissipation. Selecting snubber values requires knowing the leakage inductance and parasitic capacitance, which can be extracted from the measured ring frequency.

Ground Bounce (Simultaneous Switching Noise)

Ringing observed on digital output signals from fast I/Os in a processor or ASIC is frequently caused by ground bounce, also called simultaneous switching noise (SSN). This occurs because the ground path from the die through bond wires, package leads, and board vias carries a finite parasitic inductance. When multiple output drivers switch simultaneously, the transient current through this shared ground inductance induces a voltage across it, momentarily shifting the local ground reference inside the chip relative to the board ground. The I/O output voltage, referenced to the shifted internal ground, appears to ring when measured against the stable board-level reference.

The inductance involved is small, often in the range of hundreds of pH to a few nH, but the dI/dt value in modern CMOS drivers is large enough to produce voltage excursions that produce significant noise and can even damage components. The resulting ringing is in the MHz range and is independent of the length of the connected transmission line.

Simplified circuit diagram illustrating the primary culprit of ground bounce, which is the package/ground connection inductance in L1. Read more in this article.

The two primary solution steps are:

• Minimize the ground path inductance by using a low-impedance ground connection from the IC package to the PCB, including multiple ground vias and a solid ground plane directly beneath the BGA or QFP footprint.
• Place small, low-ESR bypass capacitors as close to the power and ground pins as physically possible to provide a local charge reservoir and reduce the loop area through which transient current must flow.

Transient Response on a Digital PDN

When a large number of fast I/Os switch simultaneously, the aggregate current step drawn from the power distribution network produces a transient voltage droop followed by ringing on the supply rail. This is distinct from ground bounce in that it represents the PDN's inability to deliver charge fast enough, rather than a shifted ground reference. The ringing frequency corresponds to the resonance between the inductive portion of the PDN impedance and the bulk or mid-frequency decoupling capacitance.

PDN impedance graph example; total impedance shown in the black line while each contributing factor is shown in the graph.

A PDN behaves inductively above the frequency where its decoupling capacitors transition from capacitive to inductive impedance. If the target impedance is violated within the bandwidth defined by the I/O switching speed, the transient response will be underdamped and ring. For a device with hundreds of I/Os pulling current from the PDN at the same time, the current step can be tens of amps with sub-nanosecond edges, placing the energy of the transient well into the hundreds of MHz range.

Example noise measurement on a PDN (yellow curve) due to I/Os switching (blue curve). Read more in this article.

The solution is to design PDN impedance below the target impedance across the full bandwidth of interest. At low frequencies, bulk capacitors and voltage regulator output capacitance dominate. At mid frequencies, discrete ceramic decoupling capacitors provide the charge. At high frequencies, plane capacitance from closely spaced power and ground planes in the stackup becomes the only effective decoupling mechanism. Achieving flat, low impedance across this entire range requires a coordinated selection of capacitor values, quantities, and placement, combined with a stackup that provides sufficient plane capacitance through thin dielectric spacing between power and ground layers.

Back-and-Forth Signal Reflections

The most common use of the term ringing in signal integrity refers to repeated reflections on a transmission line caused by impedance mismatches at the source, load, or both. When a signal edge launches down a trace and encounters a discontinuity at the far end, a portion of the energy reflects back toward the source. If the source also presents a mismatch, the reflected wave bounces again, and the process repeats with diminishing amplitude until the line settles to its final DC value.

Ringing due to reflections superimposed on a table logic level (green) and a desired signal with the ringing reduced through use of a series resistor at the source side (red). This ngspice simulation result was provided by Mahesh M P Nair, Senior Team Lead - R&D Tools at Sierra Circuits, on LinkedIn.

The period of the ringing is directly tied to the length of the transmission line, because each reflection cycle requires the wave to travel the full round-trip distance along the trace. A longer trace produces a lower ring frequency; a shorter trace rings faster. The damping rate depends on the magnitude of the reflection coefficients at each end.

The solution is proper impedance control. The trace geometry must be designed so that its characteristic impedance matches the driver output impedance and the receiver termination. Achieving this requires accurate dielectric constant and loss tangent values for the laminate materials in the stackup, combined with a field solver that accounts for trace width, copper weight, and dielectric thickness. The layer stack manager in Altium Designer includes an integrated impedance solver that performs this calculation directly from the stackup definition, ensuring that controlled-impedance traces are correctly dimensioned before routing begins.

Solve Ringing in the PCB Design Phase

Ringing across all of these scenarios can be prevented or controlled when the right design steps are implemented within your EDA environment before the board reaches fabrication. Circuit simulation allows you to verify transient behavior and snubber effectiveness early. Impedance calculation integrated into the stackup ensures transmission lines are matched from the start. Component selection tools let you find the right decoupling capacitors, snubber resistors, and clamp diodes without leaving the design environment. In Altium Designer, the relevant capabilities include:

• SPICE simulation for time-domain transient analysis of power and signal circuits
• Layer Stack Manager with integrated impedance solver for controlled-impedance trace design
• Manufacturer Part Search for sourcing components with verified parametric data and availability

Whether you need to build reliable power electronics or advanced digital systems, use Altium’s complete set of PCB design features and world-class CAD tools. Altium provides the world’s premier electronic product development platform, complete with the industry’s best PCB design tools and cross-disciplinary collaboration features for advanced design teams. Contact an expert at Altium today!

Frequently Asked Questions

What causes ringing in a PCB circuit?

Ringing is cause by interaction between parasitic or intentionally placed capacitance and inductance, creating an LC circuit with a well-defined resonance. When this equivalent circuit is disturbed, such as a with a digital signal, the circuit oscillates and this is observed as ringing.

How do you measure ringing on a PCB with an oscilloscope?

Ringing is easily measured with an oscilloscope probe between a target net and ground (for single-ended nets). For differential nets, a differential probe may be required to take the difference between the two nets with respect to ground.

What oscilloscope bandwidth is needed to measure PCB ringing accurately?

Oscilloscope bandwidths need to be selected in order to avoid Gibbs phenomenon, typically based on the rise time of the signal as detailed in this article. The exact bandwidth depends on the filter order built into the front end of the oscilloscope, which is typically unknown. For this reason, most designers will use a rule of thumb that the bandwidth must be at least 5x the clock rate of the signal being measured.

How can PCB ringing be reduced during the design phase before fabrication?

There is no single method to reduce or eliminate ringing. Different types of ringing require different solutions. For example, on a transmission line, reflection-based ringing is solved with load-side or source-side impedance matching. In a switching regulator, the solution may involve placement of an RC snubber or RCD clamp circuit.