Addressing The PDS Design Challenge

July 8, 2019 Kella Knack

In part 1 of this article, I described the various challenges and problems associated with maintaining the power integrity of a PCB as accomplished through the design of a fully functioning PDS for any given product implementation. This article will address those problems and challenges by outlining the elements that comprise a PDS, what the job of an engineer is in designing a PDS and the resources available for that design process. It should be noted that a thorough treatment of all these elements is contained in Chapters 32-37 of Reference 1 and Chapter 3 of Reference 2 noted at the end of this article.

The Root of the Problem

As noted in previous articles, power delivery has become the most critical and the most difficult aspect of today’s PCB design process. And, as cited before, this is due to the number of frequencies that have to be addressed, the huge currents and the shrinking operating voltages. While getting the routing rules and determining the stackup of a board can be accomplished in as little time as a few days, it can take up to a month to design a functioning PDS. But, because PDS design is not well understood it is sometimes left to the end of the design process, given short shrift and, when problems are encountered, becomes victim to the myths and rules-of-thumb that have no sound basis in engineering.

The Elements that Comprise a Successful PDS Design

Figure 1 is the diagram of a real PDS system. The goal of the PDS design process is to make a power source with an impedance that is low enough so that the Delta I load current changes result in a ripple voltage that is within spec. In this diagram, a power supply impedance can be seen. The product developer’s task is engineering this impedance so that it satisfies the foregoing conditions. This is an analytical problem that has to take into account a number of factors. As part of this process, noted in Part 1 of this article, the engineer has no choice but to assume that the Delta Is are what the maximum Ioads are. Further, they can occur at any frequency from DC out to several hundred MHz. 

Figure 1. The PDS Design Problem Simplified

Figure 2 shows the PDS impedance of a typical design with all of the elements that comprise a PDS.

These include:

  • Voltage regulator module (VRM) also referred to as point of load (POL). 

  • This is the module that creates the DC voltage.

  • The capacitors that are mounted on the board.

  • Plane capacitor (PCB).

Figure 2. Schematic of Typical PDS 

Each of these elements has a limited range of frequencies wherein they are effective as follows:

  • VRM: The VRM is capable of maintaining a voltage up to a few KHz.

  • Capacitors: The capacitors are capable of achieving low impedance from a few KHz up to about 100 MHz.

  • Plane Capacitor: The plane capacitor is capable of supplying those frequencies that are above 100 MHz. 

Note: The source of all EMI problems that we have troubleshot over the past few years has been the lack of any plane capacitance in the board. As an aside, it’s important to note that when boards get small there is no plane capacitance. In these instances, the capacitance must be within the IC component itself. The job of the PDS engineer is to manage the foregoing elements such that a low impedance is maintained across the whole frequency range. Note: As cited in my previous article regarding the use of ferrite beads, the necessity of maintaining a low impedance across the entire frequency range of a given PCB negates the use of ferrite beads. This is because ferrite beads in the power path destroy the impedance of the PDS as, by definition, ferrite beads are high impedance.

In truth, PDS design has become step 1 in the design process. It’s not even possible to determine how many layers are needed in a board without first having done the PDS design. This is due to the fact that the amount of plane capacitance formed by Vdd and ground planes closely spaced to each other is not known until the PDS step in the design flow has been completed. Then, this plane capacitance is built into the PCB stackup.

Impedance vs. Frequency

Figure 3 is the impedance vs. frequency using the classic .1 and .01 microfarad capacitors rule-of-thumb. The vertical axis is impedance and the horizontal is frequency. As noted in Reference 3 of this article, with the use of .1 and .01 microfarad capacitors, things gets better to about 60MHz and then things get worse. This demonstrates that arbitrarily putting capacitors onto a board leads to a bad outcome. This diagram is courtesy of University of Missouri at Rolla and is cited in Reference 3 at the end of this post.

Figure 3. Impedance vs. Frequency for a Typical Design using 0.1 uF and 0.01 uF Capacitors

Figure 4 shows the output impedance for a typical VRM. This is a DC-to-DC converter. It shows a very low impedance out to 100Hz only and then ceases to regulate. From there on out you can’t rely on the regulator to maintain a low impedance. Capacitors have to take over above that frequency. 

Figure 4. Impedance vs Frequency of a Typical Voltage Regulator Module (VRM)

Figure 5 shows the impedance vs. frequency of a typical PDS with all of the elements combined. The blue curve is the plane capacitor and the black curve is the regulator after it stops regulating. Also shown are the different values of capacitors each operating within their narrow range of frequencies. The red curve is all of the elements working together. The job of the PDS engineer is to pick the right combination so that the impedance target has been met.

Figure 5. Impedance vs Frequency of a Typical PDS

 

Power Integrity as Part of the Design Process

The steps in designing a functional PDS include figuring out what the loads are, what the ripple target is and then engineering the afore-mentioned elements. But, you are not done until you prove you have got it right. That proof is accomplished by doing the measurements as outlined in Appendix 2 of Reference 2. As noted above, the key area where people make a misstep is by not incorporating plane capacitance into the board.

As stated above, due to a variety of factors, PDS design is often the last aspect addressed during the PCB design process. Often times, engineers don’t know the right questions to ask when it comes to designing the PDS and/or they rely on the component app notes which don’t incorporate the PDS design elements. In addition to using simulation tools, there is another resource available that satisfies what most engineers will need when designing a PDS: a tool from Altera called ALTERA_PDN_Tool v.10,  and it is freely available on the company’s website. 

With the Altera PDN tool, you select capacitors from the capacitor library; you define how you are going to mount those capacitors; you define the plane capacitance; you define how you are going to hook up the BGA; and you define what the voltage, tolerance and Delta I are. The tool then does the math for you and tells you how much inductance there is down to the plane. This enables you to complete the PDS design process in the most efficient and effective manner possible.

Summary

PDS design has become the most critical and difficult element within today’s PCB design process. Understanding the elements that comprise a fully functional PDS while maintaining a low impedance across all frequency ranges of the PCB is a crucial part of this process. There are methods and tools available that can help ensure the successful implementation of power integrity in any given PCB design. Talk to an Altium expert today to learn more.

 

References:

  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 1 2003.

  2. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 2 2006.

  3. Hubing, Todd H. et al, “Power Bus Decoupling on Multilayer Printed Circuit Boards” IEEE Transactions on Electromagnetic Compatibility, Vol. 37, NO 2, May 1995.

  4. Smith, Larry & Bogatin, Eric: “Principles of Power Integrity and PDB Design Simplified,” Prentice Hall, 2017

About the Author

Kella Knack

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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