How Parasitic Inductance Can Impact Your ESD Protection
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When I was a kid, I was certain I was going to be a biologist. I collected all kinds of lizards, tadpoles, and insects, and spent most of my allowance on aquariums for my various creatures to live in. However, one thing really held me back. I am super grossed out by parasites. I will let a mantis or snake crawl all over me, but even looking at a tapeworm gives me dry heaves. Eventually, I went into engineering, where nothing needs weekend feedings. While parasitic parameters are bad news, they’ve never made me throw up at work.
In particular, parasitic inductance (L) can have a significant impact on how effective your electrostatic discharge (ESD) protection is. Managing your parasitic capacitance and using transient voltage suppressors (TVS) at your inputs are critical first steps. However, if you don’t minimize parasitic inductance all that work can go to waste. This is especially true when you’re using a TVS. If a TVS diode experiences high parasitic inductance, in the event of an ESD pulse the voltage might be allowed to overshoot dramatically and not protect your components at all.
I kept lots of little creatures, like anoles, but a strenuous aversion to parasites kept me from a career in biology.
We can work this out if you look at the inductance in a TVS protection and think way back to your introductory circuits class.
The voltage of the ESD pulse (VESD) can be considered: VESD = VBREAKDOWN(TVS) + RDYNAMIC(TVS)*IESD + LESD(dIESD/dt). If you really want to dig deep into the math, Texas Instruments has an amazing walkthrough. The key takeaway for those of us skimming this over lunch is the last term: LESD(dIESD/dt). Because it is very tiny, dIESD/dt will be huge. Even if the stray inductance LESD is very small, you can still have a huge voltage spike in the system.
So what do you do if the problem is inherent in the traces of your printed circuit board? The key is smart component placement to minimize shunt paths and the resulting parasitic inductance.
Minimize any inductance from the TVS to ground by keeping the trace short and by using direct routing. Don’t use a stub or via to connect to the ground plane, so there’s no additional path length or material to contribute to LGND.
The same is true of the input to the TVS: keep it short, don’t use vias or stubs. LESD can also contribute negatively to your parasitic inductance and protection capability. Keep the TVS close to the input connector, too. In addition to keeping parasitic inductance low, it will help prevent transient coupling of the ESD pulse into neighboring traces.
Minimize trace length and don’t use vias to connect to your TVS.
Keep the sensitive components that you are protecting further away from from the TVS. You don’t just want to keep the inductance LESD small, but you’ll also want maximize the ratio of LIC to Linput on the protection line. As Machine Design explains it, “The nonlinearity of LIC acts as a buffer to the initial peak of the ESD current pulse. This creates a substantial voltage drop toward the IC. This inductance gets smaller the closer the ESD device gets to the IC, and the voltage drop shrinks to the point where it provides no additional advantage.”
Basically, by putting your sensitive components further away from the input and TVS protection, you can get some of your parasitic resistance to work for you by decreasing the voltage spike of the ESD pulse that your components experience.
While the getting placement right is certainly not as terrifying as a worm that controls a cricket’s mind (warning: you can’t unread this), it may not be something you want to do repeatedly. If you are using similar protection methodologies in multiple products, you can design your circuits once and use modular designs to make re-use easy. PCB software, like Altium Designer®, makes modular designs simple to implement and helps you protect your PCBs. You can contact an Altium Designer representative to help you get started.