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    PCB Routing Guidelines for DDR4 Memory Devices

    Altium Designer
    |  June 20, 2018

    DDR4 Memory technology first started with battleship radio transmissions

    The United States Navy uses alphabetical designations to classify hull types. For instance, the Navy used BB as the designation for battleships and DD for destroyers. During the early 1950s—not too long after the beginning of the Cold War—the Navy outfitted the first Destroyer Radar Picket ship with special radar communications systems. The DDRs had additional radar antennas and served as early warning units.

    In the world of memory devices, the designation “DDR” has a different significance for communications systems, clocks, personal computers, smartphones, tablets, and servers. Rather than provide early warnings about potential enemy forces, DDR memory devices have evolved to change our perception of performance when it comes to circuit board data transfer, power consumption, and memory-reliant tech.

    DDR4 Deserves Special Attention

    In 2014, the fourth-generation DDR memory (DDR4) was introduced, offering reduced power consumption, increased data transfer speeds, and higher chip densities. DDR4 memory also featured improved data integrity with the addition of cyclic redundancy checks on write data and on-chip parity detection.

    With notable improvements in speed, performance, and bandwidth, DDR4 memory deserves special attention. To understand the difference between DDR3 and DDR4 devices, imagine trading your current four-door family sedan for a one-of-a-kind super sports car. Just like the super sports car runs at higher speeds and requires different aerodynamics, DDR4 offers robust signal integrity and involves high data rates.

    We can take the super sports car analogy one step further when looking at the design. Compared to the family sedan, the super sports car requires more advanced aerodynamics and carbon-fiber composites for its body and components. Similarly, PCB designs built around DDR4 memory require different routing methods than standard PCBs.

    Without specialized routing methods and attention to DDR4-specific design rules, signal quality from the transmitter to the receiver can suffer. How do you approach DDR4-specific designing from a PCB layout perspective? What rules would be best put in place for ensuring your device operates with its data as intended?

    DDR4 Design Rules

    Timing can be everything when working with sensitive signals and clock technology. Ensure your circuit board has the ability to manage its data effectively by following exemplary DDR4 PCB layout guidelines. Otherwise you may encounter your design lagging behind, or encountering repeated issues with EMI and other signal-disruptive vulnerabilities.

    You’ll want to keep in mind that data rates ranging from 1.6Gbps to 3.2Gbps, large-scale fan-outs, and higher edge rates require specific techniques to maintain the minimum bit error rates needed for signal integrity. For example, lack of attention to design rules can lead to capacitive and inductive coupling from one signal to the next. As this coupling increases, crosstalk becomes increasingly troublesome.

    To reduce opportunities for capacitive coupling, you can remove all unused via pads from your design. Decoupling capacitors between the termination voltage (VTT) and the ground will minimize inductive coupling. The VTT powers the memory and is separate from the input/output voltage (VIO) and the core voltage (VCORE).

    Clocks with digital numbers on them

    Clocks and clock-based interfaces are rampant in signal and data transmission technology

    Routing Plans for Different DDR4 Topologies

    DDR4 SDRAM operate with either clamshell topology or fly-by topology. Both topologies involve advantages and disadvantages. The clamshell topology uses less board space and two layers but requires a complex routing plan. Crowding the routing between the top and bottom layers under memory devices can lead to routing congestion and longer stub traces.

    In contrast, the fly-by topology allows for easy routing and provides the best signal integrity. However, fly-by topology—with one layer of in-line memory devices—requires more space. Ultimately, deciding which of these options is best for your layout is dependant on the need for your device.

    When setting up the routing for your PCB design, always route the same net group on the same layer. Use 45o angles rather than 90o corners and avoid T-junctions for your critical nets and clocks. Do not route memory signals closer than 0.025 inches to PCI or system clocks and make sure your routing stays a minimum of 30 mils away from the reference plane and void edges. In addition, maintain the distance between the system reset signals and other signals.

    Spacing and Length Matter

    DDR4 SDRAM require shorter routes and correct spacing for optimal timing and best signal integrity. Always avoid routing two signal layers next to each other and route signal lines over a solid reference plane. As you build your routing plan, avoid routing signal lines over voids or reference plane splits.

    Any signals related to the memory interface should route between the appropriate GND or power layers. Route the DQ, DQS, and DM signals within a given byte-lane group on the same layer to reduce or eliminate layer to layer transmission velocity differences. Because the clock signal must have a longer propagation delay than the DQS signal, the clock signal trace must have a longer length than the longest DQS trace for DIMMs. Differential clock lines have higher resistance to noise as well as other negative impacts on signal integrity.

    Screencap of Altium ’s auto-interactive router

    Strong routing software will help you to ensure that any signal intensive design can run smoothly

    To plan for the amount of spacing between traces in layout, you would use the vertical distance to the closest return path for a particular trace as a factor. The practice involves using “H” to represent the factor. Multiply that length by five to find the minimum spacing between the two clock pair or a clock pair. Remember that the Address/Command/Control and DQ/DQS/DM traces require a minimum of 3H between traces.

    To simplify matters, you can easily simulate signal integrity within AltiumDesigner®  for the design capture and board layout phases of your PCB design process. The simulator calculates the characteristic impedance of traces and uses that information, along with the I/O buffer macro-model information, as inputs.

    Altium also assists you with defining the trace widths and thicknesses of routing with its Characteristic Impedance Driven Width option within the Routing Width design rule. PCB layout has never been easier for circuit boards with volatile memory, non-volatile memory, timing and clock dependencies, or for differential pairs. Use PCB design software which can get the job done accurately and efficiently for you.

    To learn more about DDR4 PCB Layout Guidelines, talk to an expert at Altium.

    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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