For many designers, the Power Distribution Network (PDN) is a foreign and intimidating part of the PCB design process. But achieving optimal PDN performance is not as complicated as it seems. In fact, the fundamental goal of optimizing your PDN can be as straightforward as your PCB design process. How do we go about making PDN optimization less intimidating? By understanding what aspects we can control.
Understanding the Goal of PDN
The fundamental goal of designing your PDN is very straightforward - provide enough current and voltage to every load to meet their operation requirements. Ensuring there’s enough metal between each of the sources and their corresponding loads is the most critical aspect of the PCB in regards to PDN performance. But how do we get there?
Can IPC-2152 Get Us There?
For a nominal cost, IPC-2152 provides relatively straightforward guidelines on how to provide sufficient metal between sources and loads. Unfortunately, IPC-2152 only applies to the most straightforward designs, meaning a designer using IPC-2152 alone will over-design their PCB while still being unaware of problems in their design. There are several limitations as a result of solely relying on IPC-2152 presents, including:
Conservative width and via recommendations that may result in larger or more power shapes and vias than necessary.
Minimal direction on how to address imperfections in a design’s power shapes.
Lack of insight into the proper placement of associated power rails.
It’s clear that IPC-2152 does not provide enough guidance to properly optimize PDN designs on its own. How can we meet our PDN design challenges with a new level of expertise?
What You Really Need to Know About PDN
There are various aspects of most PDN designs that can be influenced by the PCB designer.
Want to learn how you can better prepare for and prevent PDN issues at the PCB level with an integrated analysis tool? Download our free whitepaper PDN Basics for the PCB Designer today to find out how.
About the Author
Signal and Power Integrity Product Manager at Altium Jeff Loyer is the Signal and Power Integrity Product Manager at Altium. Prior to joining Altium, he spent more than 20 years as an engineer at Intel, the last 10 as signal integrity lead for their server divisions. While at Intel, he led work groups which significantly impacted the industry’s high-speed PCB design practices, including work on the Fiberweave Effect, copper roughness, environmental effects on insertion loss, and insertion loss control and measurement (inventor of SET2DIL).More Content by Jeff Loyer