All About CMOS, ECL, and TTL Propagation Delay in High Speed PCBs
I still remember the 386 hand-me-down computer my parents gave me as a kid. It was useful for writing simple QBasic programs and spending hours playing computer games, but the computers of today leave my old 386 PC in the dust.
With further development of computer architecture and the demands of more modern devices, the propagation delay in logic circuits becomes an important design parameter in a number of systems. In particular, TTL propagation delay may be too long for your needs, and these days technology has moved on to CMOS logic families for high speed signaling.
Transmission Lines vs. Logic Gates
The term “propagation delay” is sometimes used interchangeably with a number of other terms and in different contexts. In describing the behavior of signals on transmission lines, propagation delay refers to the amount of time required for a signal, whether digital or analog, to travel down a transmission line from its source to its destination. This time is sometimes also called transmission delay or line delay, but these terms are much less common. The microwave community uses the term group delay as this is associated with the group velocity of a pulse envelope, a particularly important parameter when dealing with modulated analog signals.
In logic circuits, propagation delay is less about the amount of time required for a signal to travel from the input to the output. It mainly refers to the switching time and settling time, i.e., the time required for an input signal to force a transition between ON and OFF states, finally causing the output to settle at its final voltage. The output voltage from a digital circuit does not switch instantaneously due to the charged load capacitance at the output, gate geometry, mobility of charge carriers at the output, and other characteristics of the transistors in a logic gate. In other words, the propagation delay is like the sum of all times required to initiate the cascade of switching events in the circuit.
There are some tradeoffs between power consumption and propagation delay for TTL devices. TTL propagation delay is ~33 ns or less, depending on the sub-family. High-speed TTL has propagation delay reaching 6 ns, although this sub-family consumes more power than other subtypes. A good tradeoff is a device that uses low-power Schottky TTL, as this has a propagation delay of ~10 ns.
Kicking Into Overdrive With ECL and CMOS
CMOS is the standard logic family used in most ICs except in specialized applications. Compared to TTL and its sub-families, ECL is a much faster architecture with propagation delay reaching ~1 ns, and it was widely used in computing architecture for some time. The downside to using ECL is that it is an all-bipolar logic family, so it has significant power draw compared to CMOS. Although ECL and more advanced architectures provide fast data rates, CMOS is still the cornerstone of VLSI with clock rates reaching 4 GHz.
Although ECL was one of the original logic families that forced designers to confront high speed signal integrity problems, ECL in its original form is basically extinct and CMOS has become the dominant logic familiy. ECL devices were usually designed to operate with small signal swings between ON/OFF states and have correspondingly small noise margins, the negative power supply used in ECL is inconvenient when mixing with CMOS or other logic families. Eventually, ECL was used with a +5 V power supply by shifting Vcc and Vee, giving us PECL today.
CMOS and TTL Propagation Delay in Your PCB
If you're worried about propagation delay from a single gate or IO in an I/C, note that the propagation delay values specified in data sheets for integrated circuits are only correct when one output from the package switches at a time. In reality, the propagation delay increases when multiple logic circuits in a package switch simultaneously. In other words, simultaneous switching noise (better known as ground bounce) causes an increase in the component's propagation delay.
This occurs because the power lines, output lines, and gate circuit in a package have some parasitic inductance. When one gate switches, it induces some back EMF in the other gates, which limits the rate at which the output current switches between logic states. The propagation delay can increase by anywhere from 100 up to 1 ns when a large number of gates switch simultaneously. Pay attention to best practices for eliminating ground bounce (minimize use of vias and place bypass capacitors) if you also want to keep propagation delay from increasing.
High-speed devices are already complicated systems that require paying attention to a number of design rules, and overlooking some of these rules can create a number of signal problems in your device. A great PCB design package like Altium Designer® contains all the tools you need to design and verify the functionality of your next high-speed design in a unified environment. The underlying rules-driven design engine checks your design against important high-speed design rules as you layout your board.