All About CMOS, ECL, and TTL Propagation Delay in High Speed PCBs
I still remember the 386 hand-me-down computer my parents gave me as a kid. It was useful for writing simple QBasic programs and spending hours playing computer games, but the computers of today leave my old 386 PC in the dust.
With further development of computer architecture and the demands of more modern devices, the propagation delay in logic circuits becomes an important design parameter in a number of systems. In particular, TTL propagation delay may be too long for your needs, especially if you plan to exceed 100 Mbps serial data rates.
Transmission Lines vs. Logic Gates
The term “propagation delay” is used interchangeably with a number of other terms and in different contexts. In describing the behavior of signals on transmission lines, propagation delay refers to the amount of time required for a signal, whether digital or analog, to travel down a transmission line from its source to its destination. This time is also called transmission delay or line delay. The microwave community uses the term group delay as this is associated with the group velocity of a pulse envelope, a particularly important parameter when dealing with modulated analog signals.
In logic circuits, propagation delay has nothing to do with the amount of time required for a signal to travel from the input to the output. It actually refers to the switching time, i.e., the time required for a signal to transition between ON and OFF states. The output voltage from a digital circuit does not switch instantaneously due to the charged load capacitance at the output, gate geometry, mobility of charge carriers at the output, and other characteristics of the transistors in a logic gate.
There are some tradeoffs between power consumption and propagation delay for TTL devices. TTL propagation delay is 33 ns or less, depending on the sub-family. High-speed TTL has propagation delay reaching 6 ns, although this sub-family consumes more power than other subtypes. A good tradeoff is a device that uses low-power Schottky TTL, as this has a propagation delay of ~10 ns and power consumption ~2 W.
Kicking Into Overdrive With ECL
Compared to CMOS (~100 ns propagation delay) and TTL (~10 ns propagation delay) devices, ECL is a much faster architecture and is widely used in computing architecture. ECL offers propagation delay reaching ~1 ns, making it useful with GHz clock rates. The downside to using ECL is that it is an all-bipolar logic family, so it has significant power draw. Although ECL and more advanced architectures provide faster data rates, CMOS is still the cornerstone of VLSI with clock rates reaching 4 GHz.
ECL devices are usually designed to operate with small signal swings between ON/OFF states and have correspondingly small noise margins. Unlike TTL and CMOS logic circuits, ECL does not draw current spikes from the power supply. Because the current drawn from the power supply remains constant during switching, an important noise source is absent from ECL devices. ECL has a purely resistive load, meaning that its output current is relatively flat compared to CMOS or TTL logic.
CMOS and TTL Propagation Delay in Your PCB
Digital IC manufacturers typically only measure the propagation delay from a single gate and quote this measurement as the propagation delay for the entire package. The propagation delay values specified in data sheets for integrated circuits are only correct when one output from the package switches at a time. In reality, the propagation delay increases when multiple logic circuits in a package switch simultaneously.
This occurs because the power lines, output lines, and gate circuit in a package have some parasitic inductance. When one gate switches, it induces some back EMF in the other gates, which limits the rate at which the output current switches between logic states. The propagation delay can increase by anywhere from 100 to 200 ps for each additional switching gate. With CMOS devices, this is a drop in the bucket compared to the propagation delay for a single gate. With ECL or TTL, this represents a significant increase in propagation delay in packages with a large number of logic circuits.
When designing high speed PCBs, you should layout your board and route interconnects while considering the lower bound on propagation delay. If you need to synchronize multiple signal nets across your board, it may be best to use a digital PLL to synchronize serial data with an external clock. If there is an IC package in one signal net, you will need to compensate the extra propagation delay either by adjusting trace lengths or using a digital PLL synthesizer. This is arguably a preferred way to synchronize data between multiple signal nets and provide compensation.
Lack of synchronization affects more than just digital signal nets
High-speed devices are already complicated systems that require paying attention to a number of design rules, and overlooking some of these rules can create a number of signal problems in your device. A great PCB design package like Altium Designer® contains all the tools you need to design and verify the functionality of your next high-speed design in a unified environment. The underlying rules-driven design engine checks your design against important high-speed design rules as you layout your board.