Analog Signal Bandwidth and its Relation to Power Integrity
With more devices running at faster edge rates and higher frequencies, power integrity can’t be considered separate from signal integrity. In any digital PCB design, the PDN needs to be carefully engineered to provide stable power with low transient ringing. The steps required in digital systems mirror those used in analog systems, but there are some exceptions in analog systems due to the very narrow analog signal bandwidth in these boards.
Digital designers and analog designers tend to think about signal behavior very differently. Digital designers tend to worry about things like transient ringing in the time domain, as this is meant to ensure (for example) the +5 V signal fed into a transmission line is read as a +5 V signal at the receiver. Analog designers need to worry about what happens within the analog signal bandwidth—what happens at other frequencies is inconsequential. Let’s look at how to interpret a PDN impedance spectrum in the context of analog signal bandwidth and how you can design your analog PDN for power integrity.
Analog Power Integrity Design
Just like digital PDN design, an analog PDN needs to supply stable power to a downstream analog IC. Variations in the power create jitter (i.e., phase noise) in the output from sensitive analog and digital circuits. This form of noise can lead to unacceptable skew in digital signals, or unacceptable phase differences that cannot be properly compensated in analog signals. In both cases, the level of noise seen at a downstream component can’t always be compensated for or suppressed.
Similarly, both types of PDNs can experience strong transients when a component draws current from the power supply. If there is insufficient decoupling in the PDN, then these transients can produce strong voltage fluctuations which propagate to the output as phase noise. In addition, strong transients in a PDN can excite board cavity resonances (for internal power planes) that emit from the board edge, or produce strong radiated emission from the power rails (on the surface layer). Addressing both types of noise requires precisely engineering the stackup geometry, as well as engineering the PDN to have low impedance.
With digital signals, which PDN impedance value should you use? This is not so clear, as the PDN has multiple resonances due to the arrangement of parallel RLC elements in PDN models. The bandwidth of a digital signal can span multiple decades, so there is a high chance the bandwidth will overlap peaks in the PDN impedance spectrum. In contrast, analog signal bandwidth values are quite narrow, spanning a small percentage of the signal carrier frequency. Your job is to engineer the PDN so that the PDN impedance spectrum is relatively flat throughout the relevant bandwidth.
Comparing Digital and Analog Signal Bandwidth on a PDN
An example with a complicated PDN impedance spectrum is shown in the graph below.
In this graph, the target impedance value is 20 mOhms. For our example digital signal, the bandwidth overlaps several resonant peaks in the PDN. When a digital component that outputs this particular type of digital signal switches, it will draw some transient current with a Fourier spectrum that falls within this bandwidth. This means some frequency components in the transient current will see high impedance, creating a strong voltage fluctuation. Despite the fact that all PDN impedance peaks fall below the target impedance value, the net impedance seen by the signal will be approximately 31 mOhms (the sum of peak impedances from the three resonant peaks in the signal bandwidth). This creates a large voltage fluctuation in the time domain that breaks past the voltage ripple limit by ~50%.
For the analog signal in the above graph, the bandwidth is very narrow and does not overlap with any PDN resonances. Any transients produced by an analog component that draws an analog signal within this bandwidth will not produce significant ripple and will operate within voltage tolerance limits. Whether you are working with a digital signal or an analog signal, the PDN can be thought of as a filter which acts on the current signal being drawn from the power supply. The voltage fluctuation in the time domain, both for analog and digital signals, would simply be calculated using an inverse Fourier transform:
Note that the current draw must be modeled as a causal source, i.e., it must be zero for t < 0. For an analog component that only draws a single frequency component, the current draw into the PDN will oscillate at some signal at a specific frequency as the analog component runs, thus the impedance function is just a delta function. This Fourier transform is trivial and reduces to a harmonic voltage fluctuation. When we’re dealing with an analog component that draws some other repeating waveform directly from the power supply, such as a sawtooth wave, we now reduce back to the digital design situation, where signal behavior and the PDN impedance must be considered over a broad bandwidth.
Engineering Your PDN Impedance
In addition to providing significant interplane capacitance in your stackup, judicious use of decoupling capacitors is required to bring the PDN impedance peaks below the target impedance over a broad bandwidth. Engineering the impedance of the PDN requires carefully tailoring the values of capacitors while accounting for the self-resonances of the PDN. For digital signals, it is best to use capacitors with high ESR values as this will ensure the PDN resonance peaks are quite broad.
For analog signals, the Q-factor of any nearby resonances does not matter. As long as the analog signal bandwidth does not overlap with any high impedance resonance peaks, then your system will function properly and there will not be strong power fluctuations on the PDN. Any decoupling capacitors you use should simply provide less than the target impedance at the relevant analog frequency. Your goal is simply to ensure low impedance throughout the signal bandwidth. Note that systems that run at higher signal levels will generally require more capacitors to sufficiently suppress ripple.
The pre-layout and post-layout simulation tools in Altium Designer® can give you a look at signal and power integrity problems in your board. You’ll have access to a set of powerful layout and routing tools and a set of simulation tools for determining signal behavior in your board. You’ll also have access to a complete set of manufacturing planning and data management features in a single platform.