PDN Impedance Analysis and Modeling: From Schematic to Layout

Zachariah Peterson
|  Created: November 3, 2019  |  Updated: March 10, 2021
PDN Impedance Analysis and Modeling: From Schematic to Layout

Power integrity affects many performance aspects in PCBs, and ensuring power integrity in a digital design starts by ensuring the PCB layout has low PDN impedance. There are several basic aspects of PDN impedance and some basic design steps that help a designer reach relatively low impedance in a PCB. Without low impedance, power glitches can cause components in a board to operate incorrectly due to large voltage swings on the power rail.

In the past, with TTL components running at high core voltages (5 V saturation logic), it was possible to ignore many power integrity problems because the noise margins on logic circuits in these components were very large. Today's digital components generally run at 3V3 or lower core voltages with thinner noise margins and higher IO count. If you can build some reasonably accurate models for PDN impedance, you can then compare transient responses on the PDN with the power fluctuation limits in modern components, which is accomplished by keeping the impedance of your PDN within acceptable limits.

Why Conduct PDN Impedance Analysis?

The high speed and high frequency designers reading this will already know the answer to this question. However, with technological demands mounting, we’ll all be high speed and high frequency designers sooner than we like, so it is important to understand how PDN impedance affects the behavior of signals in your PCB. Unfortunately, we don’t always do the best job of placing this information in one place, so I’ll happily do this here.

In short, your PDN impedance will affect the following aspects of your circuits:

  • Power bus noise. The voltage ripple created due to transient currents in your PCB. Note that, because your PDN impedance is a function of frequency, the voltage ripple caused by a switching will also be a function of frequency. Note that these transients can arise regardless of the level of noise in the output from your voltage regulator.

  • Damping in power bus noise. Any ripple on the power bus could appear as ringing (i.e., an underdamped transient oscillation) in some cases. This is one problem that can occur if your decoupling capacitor is incorrectly sized or if you do not account for your decoupling capacitor’s self-resonance frequency in your decoupling network.

  • Required level of decoupling. Most capacitors have become insufficient for ensuring decoupling in PCBs with fast logic due to their relatively low self-resonance frequencies (~100 MHz). Therefore, designers used interplane capacitance to provide sufficient capacitance to ensure decoupling. Newer capacitors with GHz self-resonance frequencies are also available, and the combination of these is used to provide decoupling in high speed/high frequency PCBs.

  • Current return path. Your return current will follow the path of least resistance (for DC current) or least reactance (for AC current). The impedance in your ground network will vary in space, which depends in part on parasitic coupling between signal traces and the PDN. To create the tightest return current loop in the PDN, it is best to use planes to ensure minimal spreading inductance.

  • IR drop. The DC portion of your supply and return current will experience some losses due to the inherent resistance of the conductors that make up your PDN.

  • Timing jitter. Because signals have finite propagation time, the current drawn from decoupling capacitors and the regulator will take some time to reach the switching component. When these signals do reach the component, they can interfere with the output signal, effectively creating some jitter in the rise time for your signal. In general, timing jitter due to power rail noise increases with noise intensity and the length between the regulator and the component. On long power rails, this can cause timing jitter to reach on the order of nanoseconds, which could desynchronize data and increase bit error rates.

Most of these problems can be reduced or eliminated by routing power using plane layers, with power and ground planes placed adjacent to each other in the PCB stackup. When this plane pair is included, it is important to understand how to model and simulate the effects of planes on power integrity and the overall PDN impedance.

A Simplified Model for PDN Impedance Analysis

You can model the impedance spectrum of your PDN and its transient response directly from your schematic, as long as you account for parasitics in your PDN. In the model below, you’ll notice several circuit elements, but this model only contains two real components. The first is your power supply/regulator, which has some specified output impedance Z(out) and is typically an RL series. The second is the decoupling capacitor, which has an ideal capacitance of Cc1. The remaining circuit elements are parasitics. The Rs and Ls values are intended to model the inherent conductor resistance and parasitic power plane inductance, respectively. The Rp, Lp, and Cp elements account for parasitic coupling between power and ground planes (i.e., interplane capacitance).

PDN impedance analysis model
A simplified model for PDN impedance analysis. [Source]

The Lp element in the plane can be eliminated or greatly reduced by routing multiple supply/return vias into the plane pair. This is effectively what is done to supply power and ground connections to high pin count components, such as large BGAs that supply many high speed signals. Therefore, many PDN impedance models used in SPICE will ignore this element.

Before analyzing this model, you need to determine or estimate the values of the various elements in your model. The decoupling capacitor values are easy; just get them from the datasheet for your desired capacitor. The interplane capacitance is also easy to roughly estimate; just use the dielectric constant for your substrate, the area of your overlapping ground/power planes, and the distance between them in your stackup, and you know the interplane capacitance Cp. The remaining R values can be calculated using your intended trace dimensions. The L values need to be estimated from the approximate loop inductance for each portion of the circuit; these values are generally on the order of pH to a few nH.

Your goal in analyzing this model is two-fold:

  1. Determine the impedance between the + and - terminals on the right side as a function of frequency. This can be done with a simple frequency sweep.

  2. Check that the PDN impedance is less than your target impedance. Note that the target impedance is calculated using the current a switching IC will draw into the PDN and the allowed voltage ripple:

PDN impedance analysis model

Target impedance

  1. Examine the behavior of transients by adding a current source in parallel with the power supply output (put the positive terminal before Z(out)). Set the current source to supply a delta-function impulse with total charge Q shown in the equation below, or to supply a stepped current. This will simulate a burst of current propagating to a switching IC at the right end of the PDN. This is a very simple way to roughly estimate how much capacitance you would need to provide all of the transient current in the PDN.

PDN impedance analysis model

Impulse magnitude you should use to simulate the transient response in your PDN

  1. Check that the lowest frequency PDN resonance (i.e., peak in the impedance spectrum) is greater than the knee frequency for your switching ICs. The idea is to minimize ripple over the broadest possible frequency band.

Note that point #3 is intended to model the transient response due to downstream switching ICs. If you have 10 ICs that will switch simultaneously and they all draw the same transient current into the PDN, then your impulse magnitude will be a factor 10 larger, and your target impedance needs to be a factor 10 smaller. Once you’ve examined these three points, you can move on to interpreting your results and determine what design steps you can take to suppress power fluctuations in your PDN.

How to Interpret Your PDN Impedance Analysis Results

Regarding points #1 and #2, you want to check that the PDN impedance is less than the target impedance at all frequencies between the clock frequency and the knee frequency (for digital signals) or within the relevant frequency you’ll be using (for analog signals). If this is the case, and you have calculated your impedance based on the case where every IC switches simultaneously, then your PDN will likely work as intended without any resulting signal integrity problems.

Addressing the results from point #3 depends on whether the transient response in your PDN appears as an underdamped oscillation. If the transient response is underdamped, then you need to bring this oscillation into the critically damped or overdamped regime. This requires using a larger decoupling capacitor, or using a capacitor with lower effective series inductance. Your decoupling capacitor should be sized to provide the impulse charge listed above, but you can certainly try to use a larger decoupling capacitor in order to change the conditions for the lowest PDN resonance so that the transient response is overdamped or immeasurably small.

PDN transient analysis
The transient response on the PDN can be linked to impedance peaks in the PDN.

Achieving the goal in point #4 is not always possible, but you should still make an attempt. Even if you can’t meet this design goal, you’ll still be in the clear if the impedance at a PDN resonance is still less than the target impedance and there is only one PDN impedance resonance within your relevant bandwidth. If there are multiple impedance resonance peaks within your relevant bandwidth, then you might be in trouble as the total impedance seen by the transient current is approximately the sum of the peak impedances; it now becomes likely that this total impedance exceeds the target impedance.

In addition to the decoupling capacitor sizing and self-resonance issues mentioned above, the results from point #3 should illustrate why interplane capacitance listed as a requirement for properly decoupling ICs with 1 ns or faster logic (e.g., ECL). Aside from using very large decoupling capacitors with very high self-resonance frequencies (they are now available on the market), placing the ground and power planes on adjacent layers was historically about the only way to provide the required level of decoupling in a PDN. Note that, whether you increase the interplane capacitance or decoupling capacitance by using multiple capacitors (again, see the article linked in the previous paragraph), making this capacitance sufficiently large will bring the transient response into the overdamped regime, effectively eliminating it.

What About the Die and Package?

Hopefully, the astute designer has noticed that the contributions from package and die impedance have not been included in the above analysis as they are built-in to the load in the PDN. These also need to be accounted for in the PDN as they contain capacitive and inductive parasitics.

PDN impedance analysis with component die and package
PDN model with package and die parasitics.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and Printed Circuit Engineering Association (PCEA), and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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