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Avoid Common Pad and Via Problems in Your Last-Minute PCB DFM Check

Zachariah Peterson
|  Created: September 25, 2019  |  Updated: September 25, 2020

BGA, connectors, and capacitors

You’ll want to examine your pads and vias for these components during a DFM check

There are times where you’ll need to make last minute changes to your board before you send it off to a manufacturer. Similarly, you may need to modify an existing design before sending it off for manufacturing, which may require swapping components as well as slightly rearranging traces and other components. This can occur due to unavailable components or simple design mistakes that do not align with DFM. Ideally, your design rules will flag any layout changes that must accompany a component swap.

However, there are some simple design problems that may not always be flagged in every design tool. Similarly, changes in your layout that are meant to accommodate supply chain problems can fail DFM checks if not checked before sending your board to fabricator. This can occur even if design changes are electrically functional. With this in mind, let’s take a look at a few simple (and often last-minute) design choices that won’t pass DFM; these errors can be common in last-minute redesigns, and it is in your interest to check for these problems in order to avoid yet another design change or delays in fabrication and assembly.

BGAs on Components

High pin density components that are swapped in your board may carry different footprints, requiring extensive changes to the fanout and/or layout. Ideally, you should use a BGA-mounted component with the same footprint if you are forced to make a component swap during design. Anytime you modify your BGA fanout, breakout routing, and pad arrangement, you need to make sure that your soldermask dams are also changed as well. A soldermask dam, plating, or tenting on a via are all important for ensuring solder from a BGA does not wick through to the back of the board during assembly.

In particular, dogbone fanouts need some minimum soldermask dam to prevent solder from wicking during assembly. However, as the pin density increases, the size of the soldermask dam decreases to accommodate, and it becomes more likely to expand and fracture during assembly. This is one reason that stacked microvias, plated-over vias, tented vias, or VIPPO are used with higher pin density components.

Check your soldermask dam on your BGA fanout during a DFM check

Pads and Thermal Vias

Suppose you made a simple design change; you found your desired component was unavailable and you swapped a component with an alternative. You just happened to pay attention to the electrical characteristics, but you neglected to notice that the footprints are different. This is one common oversight with some connectors, many passives, and some ICs. I’ll admit that I’ve made this simple mistake when swapping a component in a 14-pin DIP package for a 16-pin DIP package.

When the component footprint decreases, you may have to change the pad size, trace routing to the pads, or pad spacing. With high pin count components like FPGAs, some SoCs, or even simpler PLDs like MCUs, the swapped component will most likely have a completely different pin arrangement. At minimum, this requires some pin swapping, but it could also require rerouting your board to accommodate the pin arrangement on the new component.

Anytime you swap components that include a die-attached paddle, watch out for the dimensions of the thermal slug you used in your design. If the footprint changes, you’ll need to change the thermal slug to match. As an example; suppose you swap a QFN28 component (5 mm by 5 mm) with a smaller QNF28 (4 mm by 4 mm) and you use a grounded thermal slug; if you neglect to change the size of the thermal slug on the board, your component pins will now short directly to the thermal slug. DRC’s in high quality PCB design software should catch this error, but it is still a good idea to check this visually.

If you swap a component with a slightly different footprint, check your pads during a DFM check

Finally, check the density of vias in a thermal slug. In general, it is better to opt for more thermal vias, but not so many that you turn your thermal slug into Swiss cheese. With too many vias, you’ll have solder wicking through the board during assembly, and your assembler will have trouble soldering your IC to your thermal slug. What is interesting is that assembly houses have figured out how to deal with thermal slugs that start to resemble Swiss cheese and can still assemble these boards, but fabricators may tell you that such a board is not manufacturable.

Copper Pour Near Components

There are times when you need to modify the size of a grounded copper pour in order to accommodate changes in components or their arrangement. If you end up changing the size of a copper pour region such that it now connects directly to a group of components, you have essentially created a huge heat sink that will interfere with soldering during assembly. Heat will dissipate into this copper pour, and it becomes extremely difficult for your solder to come to the right temperature. This is one of many causes of tombstoning during assembly.

This is not an electrically incorrect design choice, meaning you've created a closed circuit. I’ve seen boards with bypass/decoupling caps soldered directly to a grounded copper pour on the surface layer, and the board worked fine, although I'm not sure how they managed to get the component to solder properly). This is one of those examples where an electrically functional design choice violates DFA in that it can have low assembly yield.

All of these points can be easily overlooked when making quick design changes in a pinch, but a deliberate visual check by you and your fabricator can help identify these simple problems and correct them. The powerful PCB design tools in Altium Designer interface with standard and customizable design rules and constraints, which can help you catch these problems and more in your PCB layout. You’ll also have access to a complete set of fabrication planning, simulation, and documentation features in a single platform.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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