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    Backroads or Highway: Managing PCB Power Distribution with a PDN Analyzer

    Altium Designer
    |  December 29, 2017

    Traffic jam in a city street road

    Who hasn’t been caught daydreaming out the window, overlooking the lines of cars on the freeway at a standstill, wondering about easier or more effective ways of getting to your job on time? And even then, sometimes the alternate routes aren’t always the fastest—there could be road construction, or an event going on which makes you have to re-route even more. At that point, most tend to throw all hopes for getting to work on time out the window (or, if you’re living in London, start driving down the shoulder).

    Now, imagine each of the roads and every intersection or hiccup in your traffic flow as of the power network for your PCB. Your job becomes navigating through the PCB and analyze how to optimize your high-power efficiency with minimal power loss. As you aim to design PCBs that are getting smaller and smaller, the pathways for your power distribution network () get tighter. This opens up a whole slew of design concerns: how do I drive this semi-truck through a one-lane alley between apartment blocks? If the sides of my car scrape the guard walls and spark, is there anything that could catch fire?

    PCB Designers have to deal with higher concentrations of heat and noise that pose threats to sensitive components, affecting adjacent structures and the functionality of the entire system. Just like, as a kid, watching your parents parallel park into a far-too-tight spot, you, too, can distribute tolerable power with minimal distribution losses so long as you keep solid design techniques in mind.

    Merging Traffic and Managing Heat in Power Distribution

    Especially in California, one of the biggest causes for delays on a highway are people not following merge-protocols and other rules. Well, in PCB Design all of your road rules are the ICs, the microprocessors, memory modules, DSPs (digital signal processors), and FPGAs (field-programmable gate arrays). If you stray beyond the tolerance of supply voltages then you cannot expect your board specifications to be met. Some basics are a good place to start:

    1. Keep traces short and broad in order to spread out heat density.
    2. Minimize impedance by keeping bypass loops as small as possible in area and length with traces of 3:1 length-to-width ratio.
    3. Optimizing spacing between components will give the least current and heating densities.
    4. Avoid sharp angles to keep heat essentially ‘uniform’ across the board.

    Minimal loss and optimally high power efficiency go hand-in-hand with heat management. Every copper trace carrying high currents and every electrical component conducting a current are sources of heat due to electric resistance. Even passive components such as resistors, capacitors, and inductors create resistive and reactive heating, respectively. When you add to that less onboard real estate, we’re looking at more hot spots and copper perforations, leading to further increases in current densities and heating. Designs to reduce I2R have always been important, but for low voltage devices, they are critical.

    PCB  board electricity short  fire and burning
    Heat distribution is one of the most critical design considerations for your PCB layout.

    Potholes and Deer Aren't the Only Interference

    With the goal of distributing power with optimal efficiency, another type of ‘loss’ that needs to be controlled is signal loss in the form of noise and crosstalk, these are known as electromagnetic interference or EMI. The challenge is, virtually every IC is a generator of noise and every high current trace emits electromagnetic radiation that can be picked up as noise, essentially acting as antennas. Also, if signals are being switched on-and-off at 300 MHz or faster, they set off magnetic pulses that are picked up by neighboring circuits, creating crosstalk. Here are some tips to minimize EMI and crosstalk:

    • Keep RF off power distribution traces with ferrite beads and bypassing capacitors.
    • For I/O pins in the input mode, tie unused inputs to the lowest impedance rail; if possible, ground by direct short.
    • Keep non-noisy traces away from noisy components such as connections, oscillators, and relays.
    • Group noisy traces together, surrounded by ground traces. And do not run them on the outside edge of the board.
    • To reduce noise propagation, control the shape and impedance of the return path. Keep in mind, noise voltage and associated current will follow the path of lowest impedance back to the point generated.
    • Don’t run adjacent conductors in parallel.
    • Keep the spacing between signal pairs to 5 times the width of the trace.

    Managing power distribution and signal loss can seem like quite a lot to keep track of. Especially if you are designing with highly specific manufacturing requirements, it can be easy to use your experience and expertise to substitute a rule check or ignore a source of potential interference. With strong PCB design software, though, much of the work of double-checking and backtracking gets placed within the automacy of your layout software.

    Deer crossing warning sign on back road surrounded by greenery
    There aren’t always warning signs to tell you when your PCB has signal interference.

    It Is Not a Shortcut, but a PDN Analyzer™ Will Get You Where You Need to Go

    Low-voltage, high-current electronic devices challenge anyone designing PCBs to reduce distribution losses as board real estate declines and component densities increase. PDNs and advances in ICs have been keeping pace with the growing demands; yet, for all the theory and superior quality of components on the PCB, the bottom line remains: can you design a statistically robust PCB with speed and cost efficiency? The answer is a resounding yes—with the smooth muscle of power delivery network analyzers.

    Being able to model PDNs, noise propagation, pre- and post-layout, and analyze EMI fields gives back some wiggle room. To be able to evaluate thermal patterns as you look at current densities, where it necks down on the 1 V plane and where the current densities increase—the end product is power optimally distributed on the PCB and an easy run over to manufacturing. Find and resolve your PDN issues with Altium Designer®’s smart PCB design software and its visual power analysis directly in your design environment without work stoppage, special expensive tools or specialist knowledge.

    Provide yourself with the ability to analyze, modify, and re-analyze your work. If you have more questions about optimizing your and minimizing distribution losses, contact an expert at Altium today.

    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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