Comparing PDN Inductance to the Inductance of a Capacitor

In previous articles, I have touched upon the use of adjacent plane layers rather than discrete capacitors. In essence, when it comes to the successful PDN design, the ground plane and power plane have some parasitic inductance, which contributes to the overall PDN inductance. This value is then related to the PDN capacitance and is very low. For this reason, the capacitance provided by adjacent plane layers is able to support the very high switching events associated with driving transmission lines. These are the frequencies at which the discrete capacitors cease to function well.

Also, in previous articles, I described the role of the inductance of the capacitor, its footprint, the vias going from the capacitor footprint to the power planes, and how all of this comes into play to affect the overall PDN inductance. To best round out the topic, it’s important to understand why there is inductance in plane pair and some solutions to reduce its effects on signal integrity.

A Brief Review — Capacitor Inductance

As described previously, there are four major characteristics that contribute to PDN inductance.

They include:

• Decoupling capacitor self-inductance.
• The inductance of the capacitor footprint.
• The inductance of the vias going from the capacitor footprint to the power planes.
• The ground/power plane inductance.

Table 1 provides the mounted ESL (inductance) for a variety of capacitors. For all of the capacitors, the mounted ESL of the capacitor is a function of via length to the power plane pair.

Power Plane Inductance

When it comes to determining power plane inductance, there are several factors that are taken into consideration. For any given conductive material, a sheet of the inductance of that material is measured in Henrys per square. Note: A Henry is the primary unit of inductance for a component that stores energy in the magnetic field that surrounds it. A Henry is defined as the inductance for which the induced voltage  (in V) is numerically equal to the rate of change in current (in A/s). These same formulations are used in determining resistance, based on the plane's sheet resistance (Ω per square). Four different equations are used to determine the inductance of a plane pair. The first thing that is done is to determine the parallel plane capacitance, as shown in Equation 1. The reference example in Equation 1 is based on the power plane between two ground planes, as depicted in Figure 1. 

Here, there is a pair of conductors with a uniform cross-section from a transmission line with characteristic impedance Z0 (characteristic impedance). Assuming the wire is a signal trace with a width of about 3.75 mils and a dielectric thickness of 3 mils, then Z0 = 50 Ω. If the width of the signal wire is increased, the Z0 of the line will decrease. For example, a signal wire with a width of 1.0 cm (0.4 in) and the same dielectric thickness of 3 mils will have a Z0 = 1.07 Ω.

Next, the impedance of the transmission line impedance versus the capacitance can be determined using a simple LC model, as shown in Equation 2. Here, the assumption is that the transmission line has a width of 1.0 cm with losses and dispersion ignored.

Because a transmission line consists of uniform segments of capacitance and inductance, the impedance of the line can be calculated as depicted in Equation 3.

Based on the information obtained from the foregoing, it is now possible to convert Equation 3 to solve for inductance. Since the values of Z0 and C are known, Equation 4 can be used to determine the inductance of the transmission line. 

The inductance for a 1 cm long and 1 cm wide transmission line can be thought of as inductance per square since the equations will produce the same value so long as the width and length remain the same. 71.6 pH is a very small inductance compared to the ESL values of mounted capacitors.

Spreading Inductance and Its Role in Capacitor Connection Path

The inductance calculation described above for a plane pair is referred to as the spreading inductance. This quantity defines the path inductance seen by decoupling capacitors that are connected to a power plane/ground plane pair through vias. Spreading inductance accounts for the fact that current does not follow a straight line between two points in the plane pair; instead, it spreads outward in the copper, confined to a region between the capacitor via and the load via. The term is used specifically to distinguish this plane-contributed inductance from the other contributors in the loop, such as the capacitor's own ESL, the footprint inductance, and the via inductance.

To put this in perspective, consider a practical mounting scenario. A 0402 capacitor with a mounted ESL of approximately 500 pH and 1 nH inductance from vias is connected to an adjacent power/ground plane pair with a spreading inductance of 71.6 pH. The total inductance from the capacitor to the load through the planes is the sum of the mounted ESL and the spreading inductance, giving roughly 1.572 pH. The plane pair contribution is a small fraction of the total, which is exactly the behavior that makes plane-based power distribution effective at high frequencies.

Complete current path from a decoupling capacitor, through a power plane, and back to the decoupling capacitor via the ground plane.

Now compare this to a design where planes are not available and the same capacitor must be connected to a QFN or quad-pack IC using PCB traces routed from the capacitor pads to the package leads around the perimeter. Trace inductance for a typical PCB trace runs approximately 7.5 nH per inch. If the capacitor is placed 0.5 inches from the nearest power pin on the package, the trace inductance alone contributes roughly 3.75 nH to the connection path. Adding the capacitor's mounted ESL of 500 pH brings the total to approximately 4.25 nH for a single capacitor. Even with 12 capacitors in parallel, the effective inductance would be about 354 pH, which is already several times higher than the plane-based case before accounting for the fact that trace-routed capacitors rarely achieve ideal parallel combining due to unequal trace lengths and routing congestion around the package perimeter.

The difference is aproximately a factor 3 for a single capacitor, and the gap widens further at longer trace lengths or with fewer capacitors. This comparison illustrates why plane pairs are the preferred power distribution structure in high speed designs: the spreading inductance of a tightly spaced plane pair is so low that it becomes a minor contributor to the total PDN loop inductance, while trace-based connections dominate the inductance budget and limit decoupling effectiveness well before the capacitor's own ESL becomes the bottleneck.

Bringing Capacitors into The Mix

Figure 2 shows an integrated circuit mounted on a PCB with a ring of 0603 decoupling capacitors surrounding the IC's BGA package. In this conceptual example, the IC has 2000 pins and is mounted on a board with 4 power planes. There are 48 capacitors, but they can be divided equally among the four power planes in the IC package. Thus, there are only 12 capacitors for each plane.

In Figure 2, the BGA package is a 1.5” square; the IC chip is a 0.8” square, and the capacitors are placed ¼” from the edge of the package. The inductance of the power plane can be approximated using Equation 5 for the inductance of two parallel planes from an inner radius, R1, to the outer radius R2. 

At 580 pH per capacitor, the 12 capacitors in parallel would have an effective inductance of 48 pH if the capacitors are on the same side of the PCB as the BGA, and are connected to the V1/Ground plane pair. The addition of 10.4 pH for the inductance of the power planes is small compared to the capacitors’ inductance. If the capacitors are on the backside of the PCB, then vias would be needed to connect to the capacitors' SMD pads. This would bring each capacitor’s ESL value up to 1.15 nH. The 12 capacitors in parallel would have an inductance of 95 pH—nearly double its effective inductance when the capacitors are on the same side as the BGA. 

How This Affects PDN Impedance

Overall, the ground/power plane inductance adds to the overall PDN inductance and impedance. When the inductance is larger, any slope associated with inductive impedance in the PDN impedance spectrum is steeper, and resonances associated with the planes occur at lower frequencies. In high speed PCBs, this is the opposite of what we want to see in PDN impedance. In addition to interplane capacitance, this should illustrate why the use of adjacent plane layers in a PCB stackup is ideal for controlling PDN impedance to low values.

Summary

The extremely high frequency of switching events associated with today’s technologies requires a more innovative approach for dealing with PDN inductance than can be handled with discrete capacitors. The low capacitance that is inherent in power plane pairs is a much better solution for handling this inductance.

PDN behavior at very high frequencies is determined long before fabrication, during stackup planning, plane placement, and capacitor connection decisions. Altium Develop supports this kind of design‑time analysis by keeping schematic intent, stackup definitions, layout, and verification closely connected as the design evolves. Instead of discovering PDN limitations after a prototype spin, engineers can evaluate tradeoffs earlier and refine their approach while changes are still low‑cost.

Altium Develop keeps Altium‑grade design tools in a workflow tuned for individual engineers and small teams, helping you move from design through review and into release with greater confidence. 

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Reference

1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.”