How to Reduce Clock and Signal Jitter: Debugging Power Supply Noise
Low level components need ultra-stable power, and high speed digital signals need to have repeatable edge transition times. The two aspects of digital signalling are related, and you’ll need to suppress all aspects of power supply noise to reduce jitter in a digital system. During a design debug, you’ll need to gather measurements throughout your board if you want to isolate and eliminate sources of power supply noise. Here’s how you can isolate strong deterministic noise sources on the DC line that contribute to jitter.
Sources of Power Supply Noise and Jitter
If you’ve ever overlaid time-domain traces of your digital signals, then you’re familiar with jitter. This term (sometimes used interchangeably with phase noise) refers to fluctuations in edge triggering of a digital signal and in the propagation delay through a logic circuit. Jitter is intimately linked to power supply noise, where fluctuations in DC power level cause a digital signal to trigger late or early. The table below shows the principal sources of power supply noise in semiconductor devices and PCBs in general.
The last entry in the table is the one that carries the most concern as it will have the greatest effect on jitter. A value of ~1 ps/mV jitter sensitivity is often cited in PDN design and analysis. For a device with high supply level and low rise time (e.g., 3.3 V and ~1 ns, respectively), ripple-induced jitter may not rise above 15% for only 5% ripple. However, as components have gotten smaller and switching rates have increased, the tolerances on jitter and supply voltage ripple are tighter.
Reducing jitter requires suppressing the effects of power supply noise in two areas:
- On the PDN: You need to design the PDN to have low ripple in order to prevent strong jitter. If you can get down to a few mV RMS ripple voltage, then you’ve done a great job with your PDN design.
- Clock jitter: All clocks have their own sensitivity to various noise sources, which influences jitter on the clock signal output. The PDN should be designed to have low ripple anyways, but jitter in a clock signal will still create jitter on the output from a component. This is due to errors when latching and triggering bit transitions in other components.
This last point becomes more difficult when you have multiple system clocks, and you’ll need to identify the clock that has the greatest contribution to jitter. For system clocks, or multiple clock lines from a single source, you may be able to pinpoint the source of jitter at a specific component. In general, multiple clocks will contribute to transient ripple on the PDN, which then contributes to jitter elsewhere in the system. There is also a lower limit on natural jitter, which is not related to transient ripple; this can only be cleaned up by locking to a more stable reference oscillator with a PLL. Finally, there is the possibility that noise on one PDN section (e.g., at 5 V) produces noise on a different PDN section (e.g., at 3.3 V).
If you can measure jitter and power supply noise, you can identify the noise source that has the greatest contribution to jitter in your components. The principle tool you’ll need is a high bandwidth oscilloscope that can gather an eye diagram.
How to Measure Jitter Due to Power Supply Noise and Ripple
Measuring jitter is difficult with some oscilloscopes as it relies on edge triggering when looking at a waveform. Visually, jitter isn’t obvious when looking at an oscilloscope trace, and determining jitter might require manually shifting and overlaying multiple signal traces on top of each other to quantify jitter. This is why the standard method for quantifying power supply noise and the jitter it creates is to gather an eye diagram with a high-quality oscilloscope.
Once you’ve gathered an eye diagram for a specific component, you can compare this with direct measurements of ripple on the PDN in the time domain. This should be done in multiple situations as power supply noise due to transient ripple is not additive; this is a situation where PDN voltage fluctuations are represented as complex numbers that add in quadrature.
For any oscilloscope measurements of PDN ripple, use a probe with the lowest possible attenuation factor as this will prevent the probe from overstating your measured power supply noise. In addition, pay attention to the bandwidth of your scope. Transients on the PDN can have frequency components reaching up to ~1 GHz. Only use the bandwidth you need to gather an accurate measurement as this will let you see all possible glitches in the PDN ripple.
Once you’ve got a time-domain measurement, you won’t be able to see which switching component or clock is the major contributor to ripple if there are multiple active components. Instead, take your data into the frequency domain. Any strong peaks in the power spectrum will correspond to some component or clock switching at a specified frequency. You can then take steps to reduce the ripple created by the identified component, such as adding a decoupling/bypass capacitor or ensuring greater interplane capacitance on the relevant PDN.
Once you’ve isolated your sources of power supply noise and its effects in your PDN, you can implement any required design changes using the powerful PCB tools in Altium Designer®. This application gives you everything you need to create and modify PCB designs, and you’ll have access to a PDN Analyzer application. You’ll have everything you need to design powerful electronics.