Bypass and Decoupling Capacitor Placement Guidelines

Zachariah Peterson
|  Created: April 5, 2020  |  Updated: September 25, 2020
Bypass and Decoupling Capacitor Placement Guidelines

Power integrity problems are normally viewed from the perspective of the power supply, but looking at the output from ICs is just as important. Decoupling and bypass capacitors are intended to compensate power fluctuations seen on the PDN, which ensures your signal levels are consistent and a constant voltage is seen at the power/ground pins on an IC. We’ve compiled some important bypass and decoupling capacitor placement guidelines to help you use these components successfully in your next PCB.

Two Related Power Integrity Problems

Decoupling and bypass capacitors are used to solve two different power integrity problems. Although these power integrity problems are related, they manifest themselves in different ways. The first point to note is that the terms “decoupling capacitor” and “bypass capacitors” when used for power integrity are misnomers; they don’t decouple or bypass anything. They also do not pass “noise” to ground; they simply charge and discharge over time to compensate for noise fluctuations. These terms refer to the functions of these capacitors as part of a power integrity strategy.

First, consider decoupling capacitors. It is generally stated that the purpose of a decoupling capacitor is to ensure the voltage between the power rail/plane and ground plane remains constant against low frequency power supply noise, ringing on the PDN, and any other voltage fluctuations on the PDN. When placed between the power and ground planes, a decoupling capacitor is in parallel with the planes, which increases the total PDN capacitance. In effect, they compensate for insufficient interplane capacitance and reduce PDN impedance such that any ringing in the PDN voltage is minimized.

Now consider bypass capacitors. They are also intended to maintain a constant voltage within a PDN and a driving IC, but the voltage they compensate is between the output pin and the PCB ground plane. Although they are placed between a power supply pin and a ground connection on an IC, they perform a different function, which is to combat ground bounce. As a digital IC switches, parasitic inductance in the bond wire, package, and pin causes the voltage between the driver’s output and ground to increase. Bypass capacitors output a voltage that points opposite the ground bounce voltage, ideally causing the total voltage fluctuation to sum to zero.

Bypass and decoupling capacitor placement and functionality
Circuit model describing the function of a bypass capacitor in relation to ground bounce.

In the above model, there is a closed loop that includes the bypass capacitor (CB) and the stray inductance L1 on the IC package/ground connection. Note that the ground bounce voltage V(GB) is measured between the output pin and the ground plane. The remaining inductances are all parasitics, which affect the response time of the bypass capacitor to compensate for ground bounce. In an ideal model, the voltage seen by the bypass capacitor will compensate for the ground bounce voltage created by the stray inductor L1 during switching.

Bypass Capacitor Placement Guidelines

If you look at the way ground bounce occurs, it should be obvious where to place bypass capacitors. Due to the parasitic inductance in the above circuit model, a bypass capacitor should be placed as closely as possible to the power and ground pins to minimize these inductances. This is consistent with the advice you’ll find in many application notes and component datasheets.

There is another aspect to consider, relating to parasitic inductances, which is how the connection is routed to the IC. Rather than routing a short trace from the capacitor to the IC pins, you should connect the capacitor directly to the ground and power planes through vias. Be sure to comply with pad and trace spacing requirements in this arrangement.

Bypass capacitor placement
Typical bypass capacitor placement near an IC.

Why is this the case? The reason is that the ground/power plane arrangement (as long as the planes are in adjacent layers) will have very low parasitic inductance. In fact, this is the lowest source of parasitic inductance in your board. You may be able to implement a better arrangement if you can place your bypass capacitor on the bottom side of the board.

Decoupling Capacitor Placement Guidelines

After you determine the size of the decoupling capacitor you need in your PDN, you’ll need to place it somewhere to ensure it can compensate for input voltage fluctuations. It is actually best to use multiple decoupling capacitors, as they will be arranged in parallel, and the parallel arrangement will provide lower effective series inductance.

Older guidelines would state that you can place decoupling capacitors anywhere on the board. However, be careful with this as this can increase the parasitic inductance seen between the decoupling capacitor and the target IC, which increases the PDN impedance and susceptibility to EMI. Instead, for ICs with fast edge rates, you should place the decoupling capacitors closer to the target IC. The image below shows a typical bypass and decoupling capacitor arrangement near an IC. This is one optimal arrangement for high speed circuits as there will be very low parasitic inductance between the capacitors and the IC for all signal paths.

Bypass and decoupling capacitor placement in a layout
Typical decoupling capacitor and bypass capacitor placement.

Note that this is a side view and shows a seemingly odd arrangement of pads, but the connections between the planes and surface layer are the important points. Routing back into the interior layer rather than the surface layer keeps loop inductance to a minimum.

Be Careful With Modeling PDN Impedance

Remember that the PDN impedance determines the size of any transient voltage ringing on the PDN (as measured between power and ground). However, the bypass capacitors are also connected between power and ground, so they are also part of the PDN! Bypass and decoupling capacitors, as well as parasitic capacitances and inductances, will collectively determine the PDN’s impedance spectrum, creating a complicated structure of resonances and anti-resonances.

While you can find some PDN optimization tools online, they assume that all parasitic circuit elements are zero, which does not match reality. In a circuit model, it doesn’t matter how you arrange your decoupling/bypass capacitors (small to large or large to small). In a real layout, parasitics matter (as was discussed above), especially for high speed/low level ICs.

With the layout and schematic design tools in Altium Designer®, you can easily implement the best bypass and decoupling capacitor placement guidelines in your next PCB. The suite of circuit simulation tools can help give you an idea of your PDN resonance structure. You’ll also have access to a broad range of tools for managing component data and preparing for production.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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