Decoupling Capacitor and Bypass Placement Guidelines

Power integrity issues are often assessed from the power supply side, but examining IC output is equally crucial. Decoupling and bypass capacitors help stabilize power fluctuations on the PDN, ensuring consistent signal levels and maintaining a steady voltage at an IC’s power and ground pins. To assist with effective usage, we've outlined essential design guidelines for bypassing and decoupling capacitors in your next PCB. This blog explores the key differences and placement strategies for bypass vs. decoupling capacitors

Two Related Power Integrity Problems

Decoupling and bypass capacitors are used to solve two different power integrity problems. Although these power integrity problems are related, they manifest themselves in different ways. The first point to note is that the terms “decoupling capacitor” and “bypass capacitors” when used for power integrity are misnomers; they don’t decouple or bypass anything. They also do not pass “noise” to the ground; they simply charge and discharge over time to compensate for noise fluctuations. These terms refer to the functions of these capacitors as part of a power integrity strategy.

First, consider decoupling capacitors. It is generally stated that the purpose of PCB decoupling capacitor placement is to ensure the voltage between the power rail/plane and the ground plane remains constant against low-frequency power supply noise, ringing on the PDN, and any other voltage fluctuations on the PDN. When placed between the power and ground planes, a decoupling capacitor is in parallel with the planes, which increases the total PDN capacitance. In effect, they compensate for insufficient interplane capacitance and reduce PDN impedance such that any ringing in the PDN voltage is minimized.

Bypass capacitors are essential for maintaining stable voltage within a PDN and a driving IC, but they serve a distinct role compared to decoupling capacitors. Positioned between an IC's power supply pin and the ground, bypass capacitors address voltage fluctuations specifically between the output pin and the PCB ground plane. They counteract voltage spikes caused by parasitic inductance in the bond wire, package, and pin by generating an opposing voltage to reduce ground bounce. This helps ensure voltage stability by ideally balancing out fluctuations to maintain a consistent signal.

In the above model, there is a closed loop that includes the bypass capacitor (CB) and the stray inductance L1 on the IC package/ground connection. Note that the ground bounce voltage V(GB) is measured between the output pin and the ground plane. The remaining inductances are all parasitics, which affect the response time of the bypass capacitor to compensate for a ground bounce. In an ideal model, the voltage seen by the bypass capacitor will compensate for the ground bounce voltage created by the stray inductor L1 during switching.

Bypass Capacitor Placement Guidelines

If you look at the way capacitor-to-ground bounce occurs, it should be obvious where to place bypass capacitors. Due to the parasitic inductance in the above circuit model, a bypass capacitor should be placed as closely as possible to the power and ground pins to minimize these inductances. This is consistent with the advice you’ll find in many application notes and component datasheets.

There is another aspect to consider, relating to parasitic inductances, which is how the connection is routed to the IC. Rather than routing a short trace from the capacitor to the IC pins, you should connect the capacitor directly to the ground and power planes through vias. Be sure to comply with pad and trace spacing requirements in this arrangement.

Why is this the case? The reason is that the ground/power plane arrangement (as long as the planes are in adjacent layers) will have very low parasitic inductance. This is the lowest source of parasitic inductance in your board. You may be able to implement a better arrangement if you can place your bypass capacitor on the bottom side of the board.

Decoupling Capacitor Design Guidelines

After you determine the size of the PCB decoupling capacitor you need in your PDN, you’ll need to place it somewhere to ensure it can compensate for input voltage fluctuations. It is best to use multiple, as they will be arranged in parallel, and the parallel arrangement will provide lower effective series inductance.

Older guidelines would state that you can place them anywhere on the board. However, be careful with this as this can increase the parasitic inductance seen between the decoupling capacitor and the target IC, which increases the PDN impedance and susceptibility to EMI. Instead, for ICs with fast edge rates, you should place them closer to the target IC. The image below shows a typical bypass and decoupling capacitor placement near an IC. This is one optimal arrangement for high-speed circuits as there will be very low parasitic inductance between the capacitors and the IC for all signal paths.

Note that this is a side view and shows a seemingly odd arrangement of pads, but the connections between the planes and surface layer are the important points. Routing back into the interior layer rather than the surface layer keeps loop inductance to a minimum.

Be Careful With Modeling PDN Impedance

Remember that the PDN impedance determines the size of any transient voltage ringing on the PDN (as measured between power and ground). However, the bypass capacitors are also connected between power and ground, so they are also part of the PDN! Bypass and decoupling capacitor placement, as well as parasitic capacitances and inductances, will collectively determine the PDN’s impedance spectrum, creating a complicated structure of resonances and anti-resonances.

While you can find some PDN optimization tools online, they assume that all parasitic circuit elements are zero, which does not match reality. In a circuit model, it doesn’t matter how you arrange your decoupling/bypass capacitors (small to large or large to small). In a real layout, parasitics matter (as was discussed above), especially for high-speed/low-level ICs.

With the layout and schematic design tools in Altium Designer®, you can easily implement the best bypass and PCB decoupling capacitor design guidelines in your next PCB. The suite of circuit simulation tools can help give you an idea of your PDN resonance structure. You’ll also have access to a broad range of tools for managing component data, and preparing for production, as well as information on choosing a bulk capacitor vs a decoupling capacitor.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.