PCB Land Pattern Design to the IPC-7351 Standard

Zachariah Peterson
|  Created: September 8, 2020  |  Updated: September 25, 2020
PCB Land Pattern Design to the IPC-7351 Standard

Your components won’t attach to your PCB without land patterns, and it’s up to the designer to create compliant land patterns for components. One common question from new designers is: what should the pad dimensions be? Technically, the only constraints on a PCB land pattern are those imposed by fabricator DFM requirements. However, many designers opt for land patterns designed according to the IPC-7351 standard. This important standard provides requirements for SMD pad dimensions in PCB footprints.

You’re not going to get in trouble simply because you didn’t design your pads to comply with the IPC-7351 standard, but it is good to follow standards on land patterns. These standards are intended to accommodate component spacing and tolerances on component dimensions, preventing common SMD solder defects like bridging during assembly. Here’s what you need to know about designing a PCB land pattern to comply with IPC-7351, and how your design tools can help.

What’s in the IPC-7351 Standard?

The IPC-7351 standard specifies some important dimensions for creating a PCB land pattern for a SOIC footprint; these are the pad width (X), pad spacing (G), and end-to-end pad dimension (Z). The image below shows where these three quantities fit into a component footprint. There are some other parameters aside from these three, which we’ll introduce in a moment. For now, just consider that we need to calculate X, G, and Z for the PCB land pattern. The other values we need for the land dimensions can be determined from some other inputs.

PCB land pattern dimensions on SMD components from the IPC-7351 standard
First set of equations and land pattern dimensions. Here, the pitch P between pads is equal to the ideal pitch between leads on the component.

Here, the land pattern needs to be designed to accommodate the solder fillet on each edge of the lead, which is quantified with the three J values. The parameter S is measured between the outer edge of the component, and L is measured from the ends of the leads. W is simply the width of the lead portion that will make contact with the pad. The subscripts “min” and “max” refer to the minimum or maximum dimension, respectively, meaning the dimensional tolerances must be included. The C values are the tolerances for each dimension. This is all summarized in the table below.


Analogous to...


S: package edge-to-edge distance



W: lead width



L: lead-to-lead distance



Finally, F is the fabrication tolerance. A decent pick-and-place machine will have 3-sigma fabrication tolerances of 0.01 mm (about 0.4 mils). This value is comparable to each C value but is much smaller than P. To a decent approximation for components P of a few mils or longer. You can ignore F and the three C values.

Note that the IPC-7351 standard is intended to provide the general description for SMD land patterns. Still, there are other IPC-735* series PCB footprint standards that provide more specific requirements for different components. Examples include two-sided and four-sided gull-wing leads, J-leads, BGA components, and others. Take a look at this document (see the very last page) for a list of IPC-735* family standards for different components. 

What Else Is Found in the IPC-7351 Standard?

The IPC-7351 standard has created what the standard calls a “One World CAD Library” format for component information used in CAD platforms. A critical aspect of standardizing and aiding automation of PCB fabrication and assembly is enforcing some uniformity in PCB footprints. The IPC-7351 PCB land pattern standard defines a fixed Zero Component Orientation such that all CAD images have the same rotation.

Your component footprint is more than just a drawing on paper. In your CAD software, it collectively includes your PCB land pattern, silkscreen markings, any solder mask opening, and component outline defined in the mechanical layer. The CAD tools you decide to use should allow you to create all these crucial elements in your PCB footprint and your desired land pattern.

The thing to remember about the PCB land pattern equations above is that they are just suggestions. They only define minimum or maximum dimensions in the land pattern; how large, dense, or small you can make your pads also depends on your manufacturer’s DFM requirements and assembly capabilities. Although it’s rare, if your manufacturer defines a pad size that violates the bounds defined in the above equation, you should implement those recommendations as long as they do not violate some other PCB footprint standards or lead to another common SMD assembly problem.

Component Footprint Generation Can Reduce Design Time

If you have access to an IPC-compliant symbol and footprint generator in your CAD software, you can eliminate redundant calculations when creating new components. Your CAD tools should include tools to help you with the following tasks:

  • Schematic symbols: Take a look at this article from Mark Harris if you need guidance on quickly creating high pin-count schematic symbols.
  • IPC-compliant footprints: component footprint generation is a great starting point for cutting out the redundant calculations involved in creating footprints. Take a look at this article to see how you can use the component footprint generator in Altium Designer.

When you’re ready to design a PCB land pattern for a component, try working with the component footprint generator in Altium Designer®. The component footprint generation tool will help you quickly create component footprints and land patterns that can comply with all PCB footprint standards, just like IPC-7351. You’ll also have access to a complete set of 2D and 3D CAD tools for creating your layout and MCAD co-design.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA), and he previously served on the INCITS Quantum Computing Technical Advisory Committee.

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