What is Burn-in Testing for Electronics?

Zachariah Peterson
|  Created: May 6, 2020  |  Updated: December 18, 2020
What is Burn-in Testing for Electronics?

Once you’re planning for production of any new board, you’ll likely be planning a battery of tests for your new product. These tests often focus on functionality and, for high speed/high frequency boards, signal/power integrity. However, you may intend for your product to operate for an extreme period of time, and you’ll need some data to reliably place a lower limit on your product’s lifetime.

In addition to in-circuit tests, functional tests, and possibly mechanical tests, the components and boards themselves can benefit from burn-in testing. If you’re planning to produce at scale, this is best performed before ramping up to high volume.

What is Burn-in Testing?

During burn-in testing, components on a special burn-in board are stressed at or above their rated operating conditions in order to eliminate any components that would prematurely fail before their rated lifetime. These operating conditions can include temperature, voltage/current, operating frequency, or any other operating conditions that are specified as an upper limit. These types of stress tests are sometimes called accelerated lifetime tests (a subset of HALT/HASS), as they mimic the operation of a component for an extended period of time and under extreme conditions.

The goal in these reliability tests is to gather enough data to form a bathtub curve (an example is shown below). The unfortunately-named “infant mortality” portions comprises early component failures due to manufacturing defects. These tests are normally performed at 125 °C.

Bathtub curve in burn-in testing
Bathtub curve showing product reliability

Burn-in tests and environmental stress tests can be performed with a prototype board at 125 °C, or above the glass transition temperature for the intended substrate material. This will provide some extreme data on mechanical stress failures for the board alongside data on component failures. Burn-in testing comprises two different types of tests:

Static Testing

A static burn-in involves simply applying extreme temperatures and/or voltages to each component without applying input signals. This is a simple, low-cost, accelerated lifetime test. Probes simply need to run into an environmental chamber, the chamber is brought up to temperature, and the device is brought up to the desired applied voltage. This type of test is best used as a thermal test to mimic storage at extreme temperatures. Applying a static voltage during the test will not activate all nodes in the device, so it does not give a comprehensive view of component reliability.

Dynamic Testing

This type of test involves applying input signals to each component while a burn-in board is exposed to extreme temperatures and voltage. This provides a more comprehensive view of component reliability, as internal circuitry in ICs can be assessed for reliability. The outputs can be monitored during a dynamic test, giving some view of exactly which points on the board are most vulnerable to failure.

Any burn-in test that leads to failure needs to be followed up with a thorough inspection. This is especially true in stress tests for prototype boards. These tests can be time-consuming and expensive in terms of time and materials, but they are critical for maximizing the useful lifetime of your product and qualifying your design choices. These tests go far beyond in-circuit tests and functional tests, as they stress a new product to its breaking point.

Board-level vs. Component-level Reliability Tests

Burn-in tests do not refer specifically to stress tests with prototype boards—this is normally given the name HALT/HASS. Burn-in tests, alongside other environmental/stress tests, can reveal board-level and component-level failures. These tests can be performed exactly at specifications or above specified operating conditions.

Some board designers may be hesitant to accept results from burn-in tests and other stress tests that are above component specs, or outside the intended operating conditions for the board/components. The logic behind this is that the board and/or components will never see such operating conditions when deployed in its intended environment, so the test results must not be valid. This misses the point of over-spec’d burn-in tests and stress tests in general.

Burn-in and stress testing
Board-level stress testing can prevent this type of disaster in your next design.

Running these tests over-spec allows more failure points to be located. Running multiple tests in series allows you to see how these failure points arise over time, giving you a much better view of reliability. Running over-spec simply provides greater acceleration of your product’s lifetime and gives you a deeper view of the bathtub curve.

If you can address any failure points identified during an over-spec’d test, you can significantly increase the lifetime of your finished board. If you have access to supply chain data in your design software, you can easily swap out components with suitable replacements that have longer rated lifetimes. All these steps go a long way toward increasing the lifetime of your finished product.

Once you get your burn-in test results from your manufacturer and you’re planning design changes, you can quickly modify your layout and prepare for a new fabrication run with Altium Designer®. In addition to the industry-standard routing and layout features, you’ll have access to a complete set of data management, design reuse, and supply chain visibility tools that make design modification easy.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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