Pad Stack Design And The Fabrication Process—part 1

Kella Knack
|  Created: September 29, 2019  |  Updated: September 10, 2020

“Pad Stack” is a term used by PCB layout personnel and PCB fabricators to refer to all of the features associated with a hole in a PCB. The hole can be plated or unplated, through-hole or blind or buried. Components of the pad stack include the drilled hole size, the finished hole size, the size of pads plotted on the inner and outer layers, the clearances in planes through which the holes drilled in the PCB pass, and the clearances in the solder mask applied to the outer layers of the PCB.

The history of the PCB fabrication process is a varied one to say the least. This article will describe the evolution of the industry, the elements of a pad stack and manufacturability and reliability considerations. The use of thermal relief pads as part of this process will be discussed in Part 2 of this article. In addition, there will be a follow-up article which will describe what happens when you try to route two traces between the pins of 1mm pitch BGAs.

The Checkered Past of PCB Fabrication

In order to understand how the PCB fabrication industry has evolved to its current state, it’s useful to explore its history. Lee Ritchey, Founder and President of Speeding Edge states, “One of the questions that has always been levied against the PCB shops is ‘why aren’t you as good as the IC manufacturers?’ Gordon Moore once noted that it was important to consider the history of PCB fabricators. IC manufacturers came from university labs while PCB manufacturers came from automobile bumper plating shops. The skill level at these PCB fab shops was the etching and plating of metal. As a result, there was not an industry-specific technical skill for years and years in board shops. There weren’t even any chemists controlling the various plating baths.”

Ritchey continues, “Early on, Dibble was our manufacturer of choice because they did six-layer boards better than anybody else. The head plating guy there would stick a finger in the bath and taste it to decide if it was right for manufacturing the boards. From this ‘test’ he would decide if he had to put something in.”

“At another manufacturer we had these large format boards and we wanted to be sure that we didn’t use inner layers with open circuits,” Ritchey continues. “This company had banks of women who visually looked at every inner layer. When they found a short circuit, they cut it out with an Xacto knife. When they found an open, they would weld a little piece of wire on. Most of these opens and shorts came from the fact that there was nothing clean about where the imaging was being done. Dust and other particulates would get on the artwork. At one facility, there was a guy who had an ashtray on the top of his table where he inspected the film used to image inner layers.”

The State of the Industry Today

From the humble beginnings cited above, the PCB fabrication industry has matured by leaps and bounds. Ritchey notes, “Good shops have gotten better at aligning the layers. Part of the problem has always been, that during the lamination, the inner layers would shrink a little bit. Now, good shops run tests on the materials to determine how much they shrink during lamination and compensate the artwork with photo plotters. On an 18x24 panel the combination of aligning the layers and getting the drills in the right place has gotten so good that we only have to allow +/-5 mils across an 18x24 panel. That is all the accumulated error. This includes laying up the layers and getting them tightly aligned to each other.” This is not to say that the PCB fabrication process is a slam dunk by any means. For instance, the location of holes drilled in PCBs was once done without regard for how the clearances around the holes impacted the planes of the PCB. As depicted in Figure 1, when speeds were slow, placing holes so close together that the clearances in the power planes could overlap and form slots in all the plane layers did not adversely affect performance. As speeds have increased, slots in the planes can severely affect signal integrity. Even worse, when drilled holes are this close together, it is not possible to route traces between adjacent holes. This is a vital requirement for PCBs that have many signal layers. Additionally, in previous times, there was enough room between adjacent pins of a component, such as a pin grid array package or a DIP, that it was possible to make generous clearances in the planes to optimize fabrication yields without concern for signal integrity. This all meant that PCB pad stack design was not a critical part of the process.

A photograph of a green solder mask PCB with visible tracks and clearance pads showing obvious overlap between clearance pads in planes.

Figure 1. A PCB That Shows Overlapping Clearance Pads in Planes

With the advent of 1.27 mm, 1 mm and 0.8 mm BGAs and other fine pitch components, there is no longer enough room to allow manufacturing to set these dimensions without the risk of adversely affecting signal integrity. Conversely, it is no longer acceptable for the signal integrity team to make these choices without concern for degraded manufacturability and reliability.

Therefore, it is necessary for the engineering and manufacturing teams to work together to arrive at dimensions for the holes, pads and clearances that meet all of the requirements. The means for achieving this are detailed below.

The Elements of a Pad Stack

Figure 2 shows a drilled and plated hole in a PCB. This is by far the most common type of hole in PCBs. The others include blind or buried vias and unplated through-holes. These aspects will be discussed in a forthcoming article.

Figure 2. A Plated Through-hole Shown in Cross Section

The visible elements of the hole shown in this figure include:

  • The capture pads on the two outer layers.
  • The capture pads on the inner layers.
  • The drilled hole diameter.
  • The hole plating.
  • The shadow cast by the hole drilled through the PCB.
  • The clearance hole in the plane through which the hole passes.

Not shown are the clearances in the top and bottom solder masks.

The definitions of the critical aspects of the above figure are:

  • Aspect Ratio. This is the length of a drilled hole divided by its diameter.
  • Via. This is any plated through-hole that is used to either connect a signal from the surface to an internal layer or to change layers.
  • Capture pad. This is the pad used to make a connection from a trace to a plated through-hole or via. This pad “captures” the plating in the drilled hole.
  • Clearance pad. This is actually a hole etched in a plane through which drilled holes pass. It is sometimes called an antipad because plane artwork was created as a negative in early photoplotters.
  • Hole shadow. This is a cylinder whose diameter is the drilled hole diameter plus the allowance for drill wander. This shadow is cast in all of the layers and it is the surface used to calculate insulation spacing to planes or traces.
  • Plane layer. This is a copper sheet that forms one of the layers in a PCB.
  • Annular ring. This is the extra diameter of a capture pad over the minimum pad size needed to exactly “capture” the shadow cast by the drilled hole. This extra copper is used to make a connection between a trace entering a pad and the plating of the hole. It’s important to note that this connection should never be the end-on cross section of the trace. (This condition can result in joint failure during soldering.)
  • Breakout. This is the condition where the drilled hole is so far off center that it is not all contained within the capture pad. This can reduce PCB reliability by creating insulation thinner than required or by creating a butt connection (end-on) between a trace and a plated through-hole.
  • Non-functional pads. These are pads on inner layers that are not needed to connect a trace to a plated through-hole. (Non-functional pads are not needed in modern PCB fabrication operations. A thorough discussion of this is presented in Reference 2 at the end of this article).

Figure 3 shows a top down view of the structure in Figure 2.

A mechanical drawing depicting the top down view of a plated hole, with all of the nominal drilled hole size, plated hole size, maximum wander distance, capture pad size, minimum annular ring, and clearance to the nearest copper labeled.

Figure 3. A Top-Down View of the Plated Through-hole Shown in Figure 2.

Manufacturing and Reliability Considerations

In order to ensure a PCB pad stack design meets manufacturability and reliability requirements there are several factors that must be taken into account. These include:

  • Worst case tolerances build up the minimum insulation between opposing conductors (in this case, the plating in the holes and the copper of the plane layers and trace layers). They must meet the standards that apply to the engineered product. (For instance, the minimum insulation spacing for PCBs that comply with GR-86 Core, the specification that covers equipment intended for use in Telcos, is 4 mils. For most other products it is 5 mils.)
  • The connections between traces and plated through-holes or vias have to be robust.
  • The ratio of drill diameter to hole length (aspect ratio) is such that copper and the second metal used to protect the copper during outer layer etching can be reliably plated over the entire hole wall to a thickness that will withstand the stresses to which the PCB will be subjected without failing.

In addition to the foregoing, it is necessary to take into account that the drilled holes will not always pass through the PCB as specified. This can occur for the following reasons:

  • The drill can wander as the drill passes through the PCB.
  • There can be an error in the alignment of all of the film layers to each other.
  • The actual laminate itself will shrink slightly during lamination and the drill machine will have a certain amount of error as it locates each hole.
  • During lamination, the layers may not be accurately registered to each other.

When drilled holes are a little off from where they should be this is referred to as drill wander. Each fabricator has characterized its overall process and has arrived at a tolerance, referred to as drill tolerance, which is used to define the hole shadow of each drilled hole. The very best fabricators can hold this error to ±5 mils which is often referred to as TIR (Total Included Radius). Middle tier U.S. fabricators can hold this tolerance to ±6 mils while the average fabricator in Asia building high-volume consumer PCBs can hold this tolerance to ±7 mils. Clearly, when working on PCB pad stack design, the designer must know where the PCB will be manufactured in order to correctly allow for this error. For those PCBs built in high volumes, the drill wander allowance will need to be greater.

When through-hole components are soldered into plated through-holes in a PCB, the heat required to cause the solder to flow into the space between the component lead and the hole wall will cause this solder heat to flow into the power planes of the PCB at each pin where there is a connection between the component and a plane. This results in poor solder connections and the need for very difficult reworks should the part need to be replaced. In order to thermally isolate the hole from the plane and allow for successful soldering, a feature called a thermal tie is used. Part 2 of this article will discuss thermal ties, their physical characteristics and their functionality. In the meantime, consider checking more articles on my blog, which covers a wide variety of PCB design aspects, from understanding PCB material and improving signal integrity to designing PCBs to suit the needs of specific markets.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium or learn more about planning your multilayer PCB stackup in Altium Designer®


  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 2.”

  2. Ritchey, Lee W., “Should non-functional pads be removed?” Current Source Newsletter, Volume 1, Issue 1, May 2004.

About Author

About Author

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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