Designing for Testability in PCB Design: Ensure High Yield and Quality

If you remember your days in school, then you probably remember the feeling of happiness and celebration when you pass a big exam. You’ll feel the same sense of adulation when your board spin passes a barrage of pre and post assembly tests, but a complex design might not reach that stage unless you implement the right design for testability methods. There are some simple steps that can help your manufacturer identify and quickly implement important bare-board and in-circuit testing (ICT), especially on critical circuit blocks.

Implementing the right design for testability practices takes the right design software and documentation. With design for testability being so important for complex designs, it helps to understand which test structures you should implement in your board for successful bare-board testing and ICT. The right test structures and documentation can ensure your next batch of complex boards comes off the fabrication/assembly line without problems.

Design for Testability: Consider the Testing Method

Design for testability is a balancing act that requires accommodating different test methods without compromising functionality. This can be as simple as designating certain pads or vias in your layout as test points in annotating your layout/schematics to indicate intended electrical functionality (e.g., voltage, current, and resistance or impedance). In some cases, you may need to create a custom pad as a no-BOM component and designate a specific testpoint on a net in your schematic. Both methods are appropriate for most circuits that are not running at extremely high speeds or frequencies.

More advanced designs that run at high speed/high frequency, or that use specialized interconnect structures, can benefit from placing test structures that are designed for specific signal integrity measurements. If you need to ensure highly accurate interconnect impedance during design, you might want to order a test coupon with your intended interconnect structure. This is a low-cost way to validate a critical portion of your design (routing and impedance) before producing boards at scale. The complement to in-circuit testing for interconnect impedance is boundary scan (JTAG) testing.

The other aspect to consider is functional testing, which is the last line of testing for finished boards. This portion of testing is highly modular and needs to adapt to a variety of different designs. In functional testing, the actual functionality of the board is checked, which can involve varying levels of complexity. Any functional tests will need to be carefully detailed for your manufacturer and may require providing an upper-assembly test environment, embedded software, or other equipment for proper testing.

Test Points

Test points are normally used in bare board testing or ICT and are designated as critical points with specific functionality requirements. Your test points are simply electrical contacts, and your manufacturer can determine the required bare-board functionality (e.g., open circuit) from your netlist or by inspecting the schematic. During an ICT, the voltage across a leg of a circuit can be easily measured with a flying probe unit during testing, and the measurements are compared with your design requirements. Test points can be designated on pads or vias in the schematic, or they can be placed in your layout as customized pads. Be sure to annotate your schematic with any required electrical functionality for your test points.

Test Structures

This is more of a general term that includes customized pads, although test structures are normally designed for gathering precision signal integrity measurements. Simple test points like customized pads can act like stubs (i.e., antennas) at high frequencies, thus they are not desired in high frequency designs as they can radiate strongly. However, using standardized test structures allows for in-circuit signal integrity tests, and bare-board tests at high speeds and frequencies, with high accuracy.

Boundary Scan Testing

JTAG is being increasingly used in functional testing of embedded systems as a way to quickly diagnose problems on interconnects without writing any functional test code, generally by taking advantage of software from component vendors. A JTAG embedded test (JET) is a convenient way to use a standard JTAG port on a processor in an embedded system for functional testing. This allows an embedded system to be tested on first power-up without waiting for the system to fully boot.

The advantage of boundary scanning is that it reduces the reliability on test points and validation structures for examining electrical behavior. Most MCU/PLD/FPGA manufacturers have incorporated boundary scan logic and additional circuitry with the standard four-wire interface to program their devices in-system. Bringing boundary scanning into functional tests is critical for evaluating functionality of HDI boards, high layer count boards, critical components mounted on BGAs with routing on inner layers, and other modern devices.

Design for Testability With Altium Designer

The schematic design, layout, and documentation tools in Altium Designer® are ideal for implementing design for testability steps in any new PCB. You’ll also have design data management and supply chain tools you can use to ensure your PCB is manufacturable and create deliverables for your fabricator. All these features are accessible in a single design environment, which helps you remain productive and get to market quickly.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.