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    Preventing Ground Loops in Your PCB Design

    Altium Designer
    |  March 30, 2018
    Preventing Ground Loops in Your PCB Design

    I think we’ve all been there. You buy that awesome stereo system only to hear that familiar humming sound in the background. When you take it back to the store the clerk blames the manufacturer. The stereo manufacturer then blames the component manufacturer and the component manufacturer can’t blame anyone. In reality, ground loops that form due to shoddy design are the source of the problem.

    Ground loops generate noise in electric circuits. Large currents can exist in ground planes, and a voltage differential between ground connections causes the formation of a ground loop. Ringing or humming sounds in some audio systems are just one manifestation of ground loop noise.

    Why Does Ground Routing Matter Anyways?

    If you remember your Electronics 101 class, you know that all electric currents move around closed loops. On a PCB, signals are routed around the board using signal and nearby return traces. As the signal rises to full strength and moves through the board, the signal and return traces create a current loop. The strength of the induced return current depends on a number of factors. If we briefly consider a trace and its ground plane in isolation, current is induced in the ground plane through the parasitic capacitance between the trace and its ground plane.

    So why is this important? If the trace is closer to the ground plane, the capacitive impedance seen by a signal on a trace will be lower, which forces the return path to follow closer to the area beneath the trace. This means that if you want to ensure a reliable return signal to ground, your signal and return should be placed as close together as possible. Placing a signal trace closer to its ground plane will ensure lower loop inductance, which helps reduce susceptibility to EMI.By placing a ground plane below signal traces, the return signal will naturally form below the signal trace and your circuit will be complete.

    Preventing Ground Loops in Your PCB Design

    Ground Plane Connections

    When the ground plane is placed directly below the plane containing your signal traces, all of your signal traces will induce their own return path directly in the ground plane. This should illustrate the convenience of using a large ground plane to route return signals rather than routing return traces individually.

    No ground plane is a perfect conductor; it has some resistance and reactance. If two signal traces connect to the ground plane at different points, a small voltage differential can exist between these two connections. This is a major source of PCB ground loops in the ground plane. Ground loop and return path potentials tend to be on the order of microvolts, but this is still enough to cause signal integrity problems, especially in low current devices.

    PCB schematic and finished board
    Proper planning can mitigate several potential ground loop problems

    While noise that arises due to ground loops can never be completely eliminated, it can be significantly reduced such that its effects on signal integrity are minimized. Rather than connecting ground connections at different points, it is better to route traces to a ground connection with the ground plane. This minimizes any potential differential between PCB traces ground plane connections by simply reducing the distance between them.

    The ground return to the power supply should also be connected to a ground plane at a single point. When a ground plane is connected to the power supply only at a single point, the entire ground plane will be held at nearly the same potential. If the ground plane is connected to the power supply return at multiple points, ground loops can form due to the voltage differential between these connections. Using a single and proper grounding connection point eliminates these loops.

    The Right Topology

    Unfortunately, only simpler designs with low component interconnectivity will allow placement of a ground plane that spans below every signal trace. Spanning a ground plane below signal traces is generally a good idea in lower frequency devices. Keeping the area enclosed by your signal traces and the ground plane small also reduces susceptibility to external EMI.

    Spanning the large ground plane under every component may not even be desirable in high-frequency applications. For example, in high-frequency mixed-signal circuits driven by crystal oscillators, placing a ground plane directly below the signal clock creates a center-fed patch antenna. This will actually exacerbate EMI issues, and signal integrity is likely to be degraded without significant shielding.

    If you elect to use multiple ground planes, ground loops can be prevented between ground planes by using the proper topology. Rather than connecting ground planes in a ring-like or daisy-chain topology, ground planes can be connected to the power supply ground in a star topology. Daisy chaining your ground planes creates can cause ground loops between ground planes. A star topology connects each plane directly to the power supply and eliminates loops between ground planes.

    Metallic spheres connected in a start-type-shape
    Use a star topology to connect multiple ground planes

    When multiple ground planes are used in your design, take care to avoid routing traces over multiple ground planes. Traces should only be routed over their own ground plane. This is especially important in mixed-signal design. For example, if a digital signal is routed over an analog ground plane, noise coupling can occur between the digital and analog signals. This defeats the entire purpose of the star topology.

    The PDN Analyzer™ tool in Altium Designer® allows you to optimize your design so that signal integrity issues are minimized. Furthermore, the 3D PCB design interface can certainly help visualize your designs. To find out more, talk to an Altium expert today.

    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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