SAP (Semi-Additive PCB Process) – Top 5 Questions Regarding Stack Up
In a previous blog post, we took a 10,000-foot view and went through a basic introduction to SAP (semi-additive process). This refers to an additional tool in the PCB fabricators' toolbox that enables them to provide feature sizes for trace width and spacing that are 25 microns, (1 mil) and below depending on the fabricators' imaging equipment. This provides much more flexibility to breakout out tight BGA areas and the ability to shrink overall circuit size and/ or reduce the number of circuit layers in the design.
As the PCB design community embraces the benefits of this new printed circuit board fabrication technique, there are of course many questions to be answered. Today’s blog will address some of the most commonly asked questions related to circuit layer stack-up as people are introduced to this new technology.
Do all layers need to be produced with these ultra-high-density feature sizes?
It is common to use a hybrid approach utilizing both subtractive etch layers and SAP layers in the same printed circuit board stack-up. The layers do not need to be either one technology or the other. Traditional subtractive etch technology and SAP technology are simply two different approaches to creating traces. Once the traces are formed, the SAP layers are processed through the same process steps as subtractive PCB layers.
One typical approach is to use SAP layers on the layers required to route tight pitch components, often reducing the overall number of layers and also reducing the number of lamination cycles required. Then using subtractive etch layers for power and ground layers and routing layers that do not require fine feature sizes.
Does the entire layer need to have the same trace and space dimension?
No, in fact, it is common that we discuss this new fabrication technique in terms of the lower limits of the feature sizes that are able to be fabricated, but the process is not limited to only finer feature sizes. The SAP processes move the limiting factor for fabrication from the etching process to the photolithography process. Independent of the seed layer of copper selected, which may be a thin copper foil, (mSAP), or an ultra-thin layer of electroless copper (semi-additive process), the dry film resist is patterned, and electrolytic copper is then used to form the printed circuit board traces that were patterned.
The lower limits of those trace capabilities and the tolerance of the circuit traces formed vary based on the process used. The mSAP processes even with an ultra-thin copper foil, have a seed copper layer that is considerably thicker than the electroless copper seed layer used in the A-SAP™ process. Because the seed layer of copper needs to be etched where it is not required, the thicker copper will take longer to etch, which impacts the trace itself. Both the line width and space need to be larger with the stack-up mSAP process and the line width tolerance will need to be greater than with the semi-additive process.
There are signal integrity benefits to be realized with semi-additive PCB processes, not only the ultra-high density feature sizes but also with larger feature sizes. With traditional subtractive etch processes, controlled impedance is typically specified with a +/- 10% tolerance due to variations in material and process. With SAP, the line width tolerances are much more tightly controlled, and controlled impedance can be held to a much tighter tolerance.
Can outer layers and plated holes be created with SAP processes?
Yes, a PCB designer can confidently design a printed circuit board with ultra-HDI features on outer layers and also connect with reliable plated through holes, using the A-SAP™ process. When working with stack-up mSAP, circuitry on the outer layers is often discouraged.
Fabricators building with A-SAP™ have been running regular lots of material using standard d-coupons with stacked and staggered microvias to help PCB designers and OEMs feel comfortable with the reliability of the plated through holes created with the electroless seed layer of copper explained above.
Are fabricators specializing in quick turn, low volume, high-mix designs building with SAP processes, or is it primarily being built for smartphones and other high-volume applications?
We do tend to hear much more about the high-volume, Asian facilities that cater to the smartphone market. These include a handful of shops that are booked out for one to two years making it difficult for a PCB designer to prototype a new concept.
What we don’t hear as much about are the three US-based PCB fabricators that now offer the A-SAP™ process for prototype and production work: Calumet Electronics, American Standard Circuits, and FTG. There is also a handful developing the mSAP process.
How do these finer lines and spaces impact impedance?
As a little teaser…. this will be the topic of my next blog when I help break down the key elements to understand as you begin a design that requires impedance control and ultra-high-density trace and space.
In the meantime, please feel free to comment or reach out to me with your questions. We are here to help shorten the learning curve and help PCB designers understand how to best utilize this new fabrication capability.