Backplane Routing Topology for Gigabit Copper and Fiber Networks

Zachariah Peterson
|  Created: August 12, 2019  |  Updated: February 21, 2021

Ethernet ports on a PCB
You’ll need a backplane to stack multiple ports in a rack-mount unit

Many systems require some kind of copper or fiber network interface, including gigabit-capable network cards for PCs and high performance embedded systems, data centers, military, and aerospace. Greater use of fiber optic modules and expanding networking capabilities in a variety of systems will require some PCB designers to understand backplane design in order to accommodate an array of transceivers, connectors, and high speed protocols in a single unit.

If your next design requires a large number of fiber or copper inputs and transceivers on daughtercards, then you’ll need a motherboard or backplane to hold these modules in an organized manner. This important piece of equipment is critical for ensuring transceivers remain mechanically stable while maintaining electrical signal integrity, and for providing an interface with a copper or fiber network.

Some Backplane Routing and Design Requirements

There are some basic design aspects that must be considered for any high speed backplane, but the exact layout and construction of a backplane, including an optical backplane, will depend on the features used in your product:

  • High speed protocols: Different connectors and channels are used to route connections between fiber/copper transceivers on daughter cards and the backplane. Your backplane will need to be designed around these possible connections and protocols.
  • High voltage/current: Many backplanes run at high voltage, high current, or both. IPC standards should be the starting point for design and layout.
  • Application: Your design should consider the proposed application; military and aerospace products will carry different performance/reliability requirements than a civilian product.
  • Other peripherals: Backplanes can contain a number of other peripherals beyond high speed copper and fiber connections. These will need to coexist with high speed signals.
  • Standard: The current standards on backplane architectures are VITA and PICMG, which define a number of design requirements including backplane routing and topology.

Before looking at your routing topology, you'll need to address component selection and layout on the daughtercards and, in some cases, on the backplane. 

Separate Slow and Fast Signals in Backplane Routing

Any backplane might need to support a large number of signaling standards, ranging from simple SPI/I2C/GPIOs all the away up to multi-gig Ethernet and high speed SerDes channels. When selecting which signals will go to which connector pins, try to set up the board so that slower signals are kept away from faster signals on the same layer. When routing is dense, I like to keep high speed differential signals on one half of the board and low speed signals on the other half. If the board is small (e.g., 1 or 2 U), you might not have such luxury and you'll have to increase your layer count to isolate signals.

Backplane routing topology

By separating signals in this way, you can still touch all the connector pins as you route across the backplane, but you won't be inducing crosstalk from high speed to low speed signals. As we'll see below, this style still lets you satisfy a standard backplane routing topology when routing to fiber/copper transceivers and daughtercards. However, it can be challenging to get this perfect as these signals will come close to each other as they interface with various components.

Components Determine Backplane Routing Requirements

Your components for your backplane will influence how you route your board, and even how many layers you'll need. For high speed networking applications, your backplane may include onboard transceivers, an FPGA, memories, or other high speed/high frequency components. Newer optical transceivers integrate many of the important optical and electrical components required for high speed networking into a single device that sits on a daughtercard. These normally mount to the daughtercard board using a BGA, thus there will be some escape routing required to send electrical signals to the PHY layer and to the backplane connector. Thankfully, these BGAs still tend to have rather low pin count. The pin count from these integrated transceivers will determine which connectors you can reliably use to connect your transceiver daughterboard to your backplane.

BGA on a green PCB
Transceivers may mount to the board with a BGA

The logic family used in transceivers will also influence how you'll route your backplane and which signalling standards you'll need to work with. One option for transceiver components is Gunning transceiver logic plus (GTLP), which was specifically designed for use in backplane architectures. GTLP transceivers are supplied with Vcc = 1.5 V, and they have a lower voltage swing during switching. The non-backplane side of a GTLP device is still compatible with standard CMOS and LVCMOS components. These qualities, as well as availability of PLDs that use or are compatible with GTLP (e.g., ASICs and FPGAs that support differential routing) make it desirable for use in backplanes.

Copper/Optical Backplane Routing Topology

Placing an individual transceiver in a daughtercard layout or some other high pin count components on the backplane/daughtercard are no trivial matter. The backplane for connecting multiple daughtercards along with their high speed links to copper/optical transceivers should be designed with a particular routing topology, depending on the components and signalling standards you need to use.

The principle backplane routing topologies used in modern products are point-to-point and point-to-multipoint. Point-to-point is probably the simplest routing style and it facilitates standard linear buses that are useful for routing across a backplane and touching multiple connectors. These backplane routing styles used to route connections within the standard backplane network topologies: star, double star, and mesh. The choice of backplane routing topology/network topology depends on the particular application and signalling standard used in your components.

Star and Double Star

A star network is probably the most popular topology used in networking. A star network on a backplane uses point-to-point connections between a central control unit (this could be on the backplane or daughtercard) and all other nodes (in this case, connectors). A double star network is just an extension of this, where two central nodes communicate with all other nodes, and with each other. Point-to-point routing is used for routing to other connectors, although a given connector node may branch off to other connectors in a point-to-multi-point manner.

Fully-Connected Mesh

The mesh topology is only useful when the number of line-card connectors and routing density are low. Point-to-point connections are still used to build connections between nodes. In other words, a mesh topology uses point-to-point routing to route each connector to all other connectors. For this reason, larger backplanes should be implemented with star or double-star topology unless mesh is necessary for the particular application.

Backplane routing VPX network topologies

Network topologies defined in the VPX standards.

Beyond Backplane Routing Topology

There are plenty of other high speed design issues to consider in modern backplanes, and some design choices will cross over into RF territory. High speed backplanes take 

  • Noise and crosstalk: From a noise suppression standpoint, differential routing is preferable as it offers high suppression of common-mode noise. Be careful with differential crosstalk between high speed lines.
  • Isolation and your stackup: As was mentioned above, high speed signals need to be isolated from low speed signals and each other. Connectors with more pins will generally require a higher layer count in the backplane to accommodate routing between connectors.
  • Impedance control: When your PCB design tools include an integrated field solver, it's easy to account for copper roughness and dispersion when building an impedance profile for your high speed signals.
  • Via stubs and via count: This is a matter of selecting the best routing tools and ensuring consistency in your connections. Via stubs will need to be limited and backdrilled to prevent any resonance in the via stub. Via counts also need to be limited to prevent excess return and insertion loss, including insertion loss resonances.
  • Differential length tuning: For the high speed portion of the system, such as SerDes channels and Ethernet links, you'll need to apply very precise length matching. With the right set of routing tools in your PCB design software, you can get down to micron levels of precision.

If you’re in the business of designing backplanes and other designs for interfacing with copper or fiber networks, look to Altium Designer® for a full suite of design and simulation tools for any backplane routing topology. The design and layout tools are ideal for applications in high speed networking, embedded computing, and other RF devices. The data management and documentation tools can help you quickly prepare your designs for prototyping and full-scale manufacturing.

Contact us or download a free trial if you’re interested in learning more about Altium Designer. You’ll have access to the industry’s best layout, simulation, and data management tools in a single program. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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