Every electromagnetic signal, whether it's a digital signal traveling in a PCB or a wave propagating through the air between antennas, will have a finite speed. This finite speed is the propagation delay for a signal. It is an important quantity for several reasons, which are primarily found in high-speed PCB design and in RF systems design. Differential digital interfaces and phase-sensitive RF designs are the most important areas where propagation delay is important and becomes and important parameter in a PCB layout.

In this article, I'll explain exactly where propagation delay is used in some basic calculations for PCB design. We'll see shortly that the important uses of propagation delay arise when we need to ensure consistent phase response across multiple interconnects in a PCB.

Propagation delay refers to the inverse of the speed of a traveling electromagnetic signal. It is primarily used in the PCB industry to refer to signal speed, while integrated circuit designers use the same term to refer to the time required for a logic state to toggle from an input to an output. In a PCB, the propagation delay experienced by a signal is expressed in units of time per distance (inverse of speed). In other words, as long as you know the speed of light for a signal in a PCB, invert the value and you have the propagation delay.

When a PCB designer is planning a transmission line design for an impedance controlled interface, they may need to calculate the propagation delay for a signal on that line. The factors that determine the propagation delay of a signal include:

- Dielectric constant of the substrate
- The impedance value (really the geometry of the transmission line)
- The distance to the transmission line's reference plane(s)
- For a differential pair, the distance to the other trace in the pair
- Fiber weave effects in the PCB dielectric material

The simplest definition comes from looking at the speed of light in vacuum; by using your PCB material's Dk value, you can determine the signal speed:

Invert this value, and you have the propagation delay in units of time per distance. A typical value for a 50 Ohm microstrip is ~150 ps/inch, and for striplines a typical value is ~171 ps/inch; both assume Dk = 4 dielectrics. Why should a microstrip have a different propagation delay compared to a stripline? This is because of the dependence of the geometry of the interconnect. For a stripline, the routing is on the surface layer and some of the electric field lines will pass through air, so the signal speed is defined using an "effective" Dk value:

Next, we need a formula for the effectivec Dk for microstrip lines. This value depends on the geometry of the transmission line and it can be calculated from Maxwell's equations. Using the quasi-TEM theory for transmission lines, it has been shown that the propagation delay for a signal on a microstrip is as follows:

Here, *w* and *h* are the width of the microstrip trace and the distance to the ground plane, respectively. This formula can be used by hand and is known to be accurate over a range of target impedance values within the quasi-TEM limit.

More generally, there is a definition for propagation delay that can be found directly from transmission line theory. This formula for the propagation delay requires you to know the distributed circuit element values for your particular transmission line:

Once again, invert this equation and you get the propagation delay.

This equation is universally true as a quasi-TEM model, but it is not so easy to use for design. Instead, it is normally used as part of a regression model, where the distributed element values in the formula are determined through an extraction process from network parameter measurements in an experiment or simulation. The processes and algorithms used for circuit model extraction are topics for another article.

In general, you do not need to know or calculate the propagation delay for every single signal or trace connection on your PCB.

High-speed signals, whether they are on source-synchronous interfaces, on parallel buses, or on serial differential pairs, need to arrive at a receiver within some timing margin. In general, when the rise time of the signals are faster, the timing margin will be smaller. This means that the propagation constant must be known in order to apply length tuning, which ensures signals arrive within the required timing margin.

The main timing constraint that determines whether a high-speed interface will work is the timing mismatch between two signals, which we will call Î”t. The relationship between the allowed length mismatch and the allowed timing mismatch is given by:

This length mismatch/timing mismatch arises in three important instances:

- Between signals in a parallel bus (such as DDR)
- Between two traces in a differential pair
- Between multiple differential pairs

As an example of length tuning applied in a real situation, I like to show the below image of a CSI-2 interface on an FPGA with its escape routing. The image below shows five differential pairs (4 signal lanes and a clock lane) that make up a CSI-2 interface, which would normally be routed into a camera connector. We can see one length tuning section applied in the differential net AWR_3_CSI2_TX0, which ensures that the timing mismatch between these two traces is minimized. Because the design software knows the allowed timing mismatch (it's selected by the designer) and the propagation delay (it's set in the design rules), the PCB layout tool can check for a length mismatch by automatically applying the above formula.