Ethernet Layout Routing Guidelines and Standards: MAC, PHY, and RJ-45 Connectors

Zachariah Peterson
|  Created: July 1, 2019  |  Updated: February 22, 2023
Ethernet Layout and Routing Standards: MAC, PHY, and RJ-45 Connectors

Ethernet over copper is likely part of the backbone of your office building’s networking infrastructure. Thankfully, Ethernet routing standards make it easy for designers to create everything from complex networking equipment to single-board computers for any application. The overall architecture for creating Ethernet-capable devices is deceptively simple, but certain rules should be followed to ensure signal integrity.

High-level Ethernet Layout, Routing, and Architecture

Within the IEEE 802 standards, Ethernet devices contain three primary elements, all of which must be routed together in a specific manner:

  • Medium access control (MAC): The MAC is typically integrated into the processor of the device (FPGA, ASIC, MCU, or other component), or it may be present as a standalone controller. For high port count switches there are dedicated controller ICs for this function. The MAC provides control over determining destination addressing, sends along its own address to receive data, and duplexes and assembles data into packets for transmission to another device.
  • Physical layer (PHY): The next stage in Ethernet layout routing is the PHY. This is typically an integrated circuit that converts the digital data from the MAC into analog signals for transmission down copper or optical fiber. Again, this could be integrated into the switch controller. If a switch controller only includes limited PHY space for a specific port count, the port count can be expanded with a dedicated PHY chip.
  • Magnetics circuit: Ethernet channels implement a magnetics circuit that provides isolation as stated in the 802.3 standard. The magnetics must also be terminated (Bob Smith termination as described below).

The image below shows an example portion of a layout for an Ethernet switch. This high port count switch uses a main controller ICM that includes the MAC and integrated PHY layer. This type of switch controller will typically support about 16 ports. The expansion PHY chip connects to one of the port outputs using an MII routing standard, and this chip provides the additional ports needed to increase the total port count of the switch. If you're using this system layout, pay attention to the required MII routing standard between the main controller and the expansion PHY.

Example Ethernet layout

If you're routing an Ethernet port to a processor, you generally won't have dedicated PHY chips or controllers. MCUs that support Ethernet (e.g., Microchip's PIC32 MCUs) will generally include an integrated MAC/PHY transceiver on the die, giving you a small footprint option. If you have an MCU that supports USB but not Ethernet, there are USB to Ethernet data converters that will let you route to an Ethernet port.

Ethernet PCB Routing

The standard routing protocols for Ethernet (MII and RMII) are compatible with 10Base-T and 100Base-TX, although similar routing standards are designed for 1 Gbps and higher data rates (GMII, RGMII, SGMII, QSGMII, I cover these in the article linked above). Routing uses 50/100 Ohm single/differential impedance, requiring impedance controlled routing over a ground plane. All routes within this scheme should be placed on a single layer with precise length matching. Next we need to consider routing between different chips in the system, and to the connectors.

Routing From the Controller IC/PHY

Normally, microstrips are used on the surface layer, but striplines can also be used. If you're designing a network switch with high port count, the controller ICs may have a BGA footprint, so you'll need an escape routing scheme. Normally dog bone fanout is fine; the pitch on these components is not super-fine and you'll be able to reach the first two rows of balls on the surface layer (see above).

Routing between the MAC and PHY follows either the MII or RMII routing standards with point-to-point topology. The primary difference between these two routing standards is the number of signals required to interface between the MAC and each PHY chip. In a multi-port device, two signals from the MAC can be shared among multiple PHY chips, while another 16 signals (MII routing) or 6-7 signals (RMII routing) are required per PHY chip. Obviously, the number of signals required to reach a large number of PHY chips quickly becomes unmanageable, thus RMII was developed to reduce the total number of signals by a factor of 2.

The output from the PHY (whether integrated in the processor, from a controller IC, or from a standalone expansion PHY) connects to an RJ-45 connector through a magnetics termination circuit. Each connector receives RX and TX differential pairs routed in the standard way. The magnetics RJ-45 connector requires a specific termination scheme (see below) to preserve signal integrity.

With optical fiber networks, the output from the PHY connects to a separate fiber transmitter/receiver with its own layout rules. Commercially available transceivers are available to connect to your PCB through SFP connectors. These optical transciever modules are hot-swappable and may be accessible through a cage, as shown on the media converter card below.

Pluggable media converter card

Fiber optic media converter with an RJ-45 connector

Routing and Bob Smith Termination for RJ-45 Connectors

The routing requirements between the PHY chip and RJ-45 connectors involves groups of TX and RX lines routed as differential pairs, and these traces should be length matched and symmetric. There is also a specific coupling and termination circuit that must be placed between the PHY and the RJ-45 connector, commonly termed “magnetics” within the Ethernet layout routing standards. A magnetics termination circuit involves four transformers for a single RF-45 connector, two on each RX and TX differential pair.

One transformer is placed as a common mode choke, while the other is placed upstream (towards the PHY). Tapped ferritic transformers with 1:1 turns ratio are normally used to provide the required common mode noise rejection in the TX and RX differential pairs that connect the termination circuit to the PHY and RJ45.

RJ-45 termination schematic)

Example industrial-grade magnetics termination circuit for an RJ-45 connector. Source: Renesas

Some application notes will recommend not placing a ground plane beneath the differential pairs. However, EMI susceptibility can be reduced by connecting common mode capacitors between the RX/TX traces and ground, in which case the analog ground plane should extend beneath these differential pairs. The differential pairs are impedance matched throughout the termination circuits (See R3 and C above, called Bob Smith termination).

Note that some RJ-45 connectors include this second transformer or both transformers as part of an integrated magnetics circuit (magjack connector). Always check the datasheets for integrated connectors to see what other components need to be added to complete the termination circuit. If these transformers and associated passives are not integrated, Ethernet transformer modules are also available as discrete components (usually in SMT packages). These discrete modules provide better ESD protection as there will be larger separation between each portion of the system.

However, the advantage of the integrated magjack is that these separate ground regions are not needed. Instead, the system ground should run right up to the edge of the connector with all routing provided directly over the ground plane. This is done in the example below, where a single Ethernet switch controller IC is providing signal to a 2x6 RJ-45 magjack array; ground is completely placed on L2 right up to the edge of the connector body. The connector housing is connector to chassis (the SHIELD net) through a ground ring along the edge of the board.


A Note on Bob Smith Termination

There has been some debate as to whether Bob Smith termination is the best termination scheme for Ethernet routing. I've discussed this in a more recent article on my own site and here on Altium's PCB Design Blog. You can read the article here. If, for some reason, you don't want to use Bob Smith termination, be sure to test your channels thoroughly on a prototype to ensure your layout and routing will work as designed. Blindly following or ignoring standards doesn't guarantee your design will work, so be sure to test the design to ensure compliance with routing and EMI/EMC standards.

PCB Stackup for Ethernet-Capable Boards

Finally, we can’t ignore the layer stack for Ethernet-capable PCBs. 2-layer or 4-layer stacks are generally used, although you could certainly use a higher layer count. In lower layer counts, power islands are generally used with a ground plane on the same layer. These planes should be decoupled with an appropriate capacitor. I haven't shown this explicitly, but the layout shown above does include a dedicated power regulator with caps placed near the controller and expansion PHY chips for decoupling.

The example below shows a 6-layer stackup that I've used for Ethernet switches. This PCB stackup can provide the required routing channels for accessing the inner balls on a controller IC with BGA footprint. This type of stackup will support a switch IC with a dozen or more ports without cramming signals into an excessively small space. The dedicated PWR layer will provide a dedicated layer to route the multiple rails that are typically needed on Ethernet switch controller ICs.

Example 6-layer stackup

EMI and Ground in Ethernet Routing

Copper pour can also appear on the surface layer to provide extra shielding against EMI for critical circuits, which is may be desirable if your device will be deployed in an electrically noisy environment or if your design includes some other RF circuits. Be careful with this, however, as placing ground pour near the controlled impedance lines will alter their impedance if the pour is placed too close to the lines. The dependence is nonlinear, as I've shown with field solver data in this article.

Note that if you place ground pour on the surface layer, it should be connected to the lower ground layer, ideally with a periodic array of vias. Only place copper pour on the surface directly over a ground plane in the next layer. This is one strategy to deal with EMI/EMC compliance, but you don't need super-tight pitch if you are using a via fence to provide EMI suppression since you're only working at 100's of MHz.

When routing on the surface layer, you may need to route a signal over a ground plane and a power island for a single interconnect. This is generally a bad idea in any device as the portion of the trace that is not placed over a reference plane can radiate strongly, and the overall circuit it forms will have large loop inductance. To provide a return path and properly switch reference planes during routing, place a small capacitor (usually ~10 nF) between the ground plane and the power island that runs parallel to the trace.

More on Ethernet Routing, Layout, and System Design

If you still want to learn more about Ethernet routing, including modern gigabit Ethernet interfaces, read this excellent tutorial from Mark Harris. In that article, he gives a deeper dive into system-level design and the particulars of gigabit Ethernet, as well as some useful tips for layout and routing. Between these articles and some good reference designs from component manufacturers, you'll be well on your way to designing with Ethernet routing.

When you use a design platform like Altium Designer, you’ll have all the Ethernet layout and routing tools you need to design copper and fiber optic-capable networking devices. The schematic design, layout, routing, and many more features are all accessible within a single unified design interface. You’ll also have access to the industry’s best signal integrity and documentation features in a single program.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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