Follow Your Multilayer Ground Return Path to Prevent EMI

Zachariah Peterson
|  Created: November 10, 2019  |  Updated: September 25, 2020
Follow Your Multilayer Ground Return Path to Prevent EMI


Following the path back to ground can quickly become complex in a complicated multilayer PCB. When your PCB has a small layer count (e.g., a 4-layer board with two plane layers), it becomes rather easy to determine the return path and deliberately design it to prevent EMI. The situation becomes more complicated when you’re working with higher layer counts. Multiple plane layers and conductors can form the ground return path, even if the conductor is not grounded. This is where it helps to distinguish between ground planes and reference planes as both can form part of the return path in your PCB.

Ground Return Path vs. Reference Planes

Reference planes are an inherent part of the signal transmission path. Whether they are intentionally placed in your board, such as a ground plane for signal traces, or an unintentional reference plane that lies close to the signal traces, can be difficult to determine if you do not carefully track the location of signal traces throughout your board. The ground return path for a signal may not actually flow through ground; it could pass through the chassis, a power plane, or some other grounded conductor.

No matter where the return path runs in your board, it will always try to get back to the low potential point on the board, i.e., the ground return point back to the power supply. Whether the return signal is induced in your chassis, power plane, or other conductor, it will be drawn back to ground due to the potential difference between your ground conductor and a conductor held at higher potential.

Aside from being a characteristic of ringing as a signal propagates, a signal’s return path determines the following behavior:

  • EMI susceptibility. The loop inductance created by a return path determines a circuit’s susceptibility to EMI. A circuit with a large current loop will have larger parasitic inductance, making it more susceptible to radiated EMI. The loop inductance is lower when the loop is tighter. This is one reason why high speed signal traces should be routed close to a reference plane on an adjacent layer.

  • Interference in mixed-signal boards. The parasitic capacitance between a signal-carrying conductor and its nearest reference conductor, as well as the loop created by the circuit, determine the reactance seen by a switching signal. Because reactance is a function of frequency content in your signal, the signal return path becomes more difficult to predict at moderate frequencies. Read this guide to learn more about designing a mixed signal return path for a single plane layer.

  • Common-mode noise path. Common-mode noise, once induced in a given trace, will try to follow the same path as your signal back to ground. The exact ground return path followed by common-mode noise depends on its frequency content as this determines the reactance seen by the signal.

The situation becomes more complicated when we are routing in a multilayer stackup with multiple plane layers as the reference conductor can change along the signal path. The primary quantities that determine the initial reference plane are the parasitic capacitance between the signal trace and nearby conductor and the circuit’s inductance. Note that the parasitic impedance is not localized to adjacent conductors thanks to inductance, which can create a complicated ground return path in a multilayer board.

Ground return path in a multilayer PCB

Can you track the ground return path for these traces?

Getting Back to a Solid Ground Return Path

If you’ve read what I’ve written above and you’re still wondering what happens to the return current in a complex PCB, you’re probably asking yourself: what happens when the current is coupled to a ground plane or other grounded conductor? Why would this happen in the first place? Both are valid questions.

Parasitics Between Adjacent Conductors

Let’s address the second question first as it helps explain the answer to the first question. The location where the return path is introduced depends on the capacitance between the signal trace and adjacent conductors, as well as the self-inductance for the circuit formed by the signal trace and the conductor in question. Together, these quantities determine the impedance seen by the signal.

The path with the lowest impedance (note, that this path can point through the substrate or through air!) is the direction the return current follows. It just so happens that the path that presents the lowest impedance (i.e., strongest coupling) between the signal trace and the candidate conductor happens to be the closest conductor as this path usually provides the largest capacitance and smallest inductance.

Power Planes as a Ground Return Path

This explains why a power plane can act as a reference conductor if it is closer to a given signal trace than the nearest ground plane. The capacitive/inductive impedance between the power plane and the signal trace may be much larger than those values between the trace and its nearest ground plane. The story we’ve told here effective describes how a signal can change reference planes as it traverses more than one layer in a multilayer PCB.

Ground return path in a multilayer PCB

Example return path for a signal traversing a power plane in a multilayer PCB.

Now for a third question: how does a return signal coupled to a power plane get back to a grounded return path? The power plane and ground plane layer will have some interplane capacitance, which allows the return current to couple back into the ground plane. In the case where bypass capacitors are connected between a power port and the ground plane, they will also contribute some capacitive and inductive impedance for a return signal induced in the power plane.

The astute designer should realize that, in general, you should not route over a power plane unless you can ensure low impedance coupling back to GND for the return path, particularly in high-speed/high-frequency boards. You should always design your board with the return path in mind in order to reduce EMI. Typically, the return path when routing over a PWR plane would be provided by nearby decaps, any vias bridging ground regions, or as capacitively coupled displacement current from the PWR plane to the GND plane. The danger here is that the return path is difficult or impossible to track through the board, especially in 4-layer stackups, which will create a strong source of EMI due to creation of a large current loop and/or high impedance return path.

The powerful PCB design tools in Altium Designer® now include a ground return path checking tool built into the DRC engine. This allows you to define limits on the deviation between a trace and its nearest reference plane as a design rule. This is then checked automatically by the routing features in Altium Designer as you create your layer. You’ll also have a complete set of tools for analyzing signal integrity and preparing deliverables for your manufacturer.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

Learn more about return path checking in Altium Designer

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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