High-Speed Signal Routing: The 5 Important Constraints
Your modern digital board is most likely classified as high speed, regardless of whether you looked at the datasheets for your components. Designing your board successfully will take some important steps when you begin your design. Aside from floorplanning and stackup design, your routing strategy will need to operate within some important constraints.
After you capture your schematic as an initial layout and create an initial component arrangement, it’s time to define your routing constraints. Doing this early will allow your DRC engine to spot rules violations before you finish your layout. Likewise, you’ll be able to modify the default rule set to meet your layout requirements. Here are the important routing constraints you’ll need to check before you start routing your board.
High-Speed Signal Routing Constraints
When working with high-speed signals, your high-speed signal routing strategy and constraints will be major determinants of signal integrity. If you can define the right design constraints, then you can prevent common signal integrity problems in the following areas:
- Crosstalk: this is related to trace spacing and geometry;
- Reflections: this is related to impedance tolerances and termination;
- EMI susceptibility: this is related to the loop inductance for your traces;
- Transient ringing; this is often used interchangeably with reflections as the two signal integrity problems look similar, but they are different. This is related to the loop inductance and any parasitics in the board.
Here are the important high-speed signal routing constraints that will help your high-speed board operate properly. As we will see, many of these important constraints center around building an accurate impedance profile for your board.
Impedance Variation Constraints
As most traces in your high-speed board are likely to be longer than the transmission line critical length, you’ll need to use impedance control to ensure signals are received without reflection. I’ve mentioned a number of signal integrity problems impedance mismatches creates, but the most important is the back-and-forth reflection that occurs on electrically long lines when impedances are mismatched.
Your signalling standard will define some permissible impedance mismatch between a source, transmission line, and load, and this should be defined when building your layer stack. As part of impedance controlled design, you can define the allowed tolerance of a line as a design rule in your layer stack manager. Once you’ve defined this controlled impedance profile, these constraints will be available in your design rule manager and routing tools.
Trace Spacing and Width Constraints
Trace spacing will determine the strength of inductive and capacitive crosstalk in high-speed designs. If traces are too close together, crosstalk will be too large. For differential pairs, if you place each end too far apart, then the differential impedance will be too low. If you calculated the correct impedance profile using an electromagnetic solver in your stackup manager, then you’ll be able to use this impedance profile to define variances in your trace width and spacing.
Determining your allowed variations in width is also an important point. You can set these deviations manually if you have done some calculations on your own, or if your traces are shorter than the critical length. Otherwise, it is best to link this to your impedance profile for your board to ensure your traces meet their impedance targets.
Return Path Constraints
The return path in your PCB will determine the overall loop inductance for a circuit, and keeping track of your return path is a critical aspect of your high-speed PCB. Even if you have experience tracking the return path in your board, it still helps to define a constraint relating the allowed deviation between a signal trace and its reference plane.
Because the return path in your board determines the overall impedance seen by a propagating signal, the relevant return path constraint must be defined from your calculated impedance profile. The allowed deviation from your target impedance determines the allowed variation in distance from your reference plane. In general, a larger allowed impedance variation creates a larger allowed return path deviation constraint in your board.
Trace Length and Length Mismatch Constraints
Length matching constraints are formulated to address two possible signalling problems:
- Excessive loss: any signal will experience loss along the trace due to attenuation and resistive loss to copper. The total attenuation along a trace can reach several dB at high frequencies (~1 GHz and above) and over long traces. A typical benchmark is to use the insertion loss at the high frequency band edge to define a limit on the total length.
- Permissible skew between traces: data is often sent between components on multiple lines in parallel. Differential pairs also require strict length matching to ensure common-mode noise cancellation. Multiple differential pairs can be used to route data in parallel (e.g., the input of some serializer components). In all these cases, a length mismatch constraint must be enforced to ensure parallel data arrives at its destination simultaneously, and that differential pairs provide the desired common-mode noise cancellation.
When you have a system clock that needs to be synchronized with a number of other digital lines in your system, length matching can get quite complicated. This requires accounting for the gate propagation delay, the signal propagation time along an interconnect, and then comparing these between interconnects. Which trace length do you take as the maximum value?
In this case, where you have multiple digital signals moving between components throughout the board, the device will not use a system clock. Instead, embedded clocking or source synchronous clocking is used. These are the standard methods for removing redundant clock signals when working with different computer interfaces (e.g., DDR, PCIe, etc.).
Signal Behavior Constraints
This last category is quite broad as there are many sources of signal distortion in any PCB. In addition, transient signal behavior or crosstalk can produce overshoot/undershoot. In addition, even if you do have an accurate impedance profile, parasitics can alter the impedance of particular traces and produce strong reflective ringing.
The exact limit on overshoot/undershoot depends on your noise margins and the size of the undefined region at your receiver components. In general, lower signal level components have lower noise margins, requiring lower overshoot/undershoot. If you include these important signal behavior constraints in your design rules, you can identify nets with strong transient behavior that leads to overshoot/undershoot. You can then take steps to apply termination schemes or redesign particular traces to have lower ringing.
High-Speed Signal Routing in a Unified Environment
All these activities are much easier when you work with a design platform where everything is integrated into a single design environment. Your routing tools need to flag violations as you create your layout, rather than forcing you to run repeated DRCs in batches.
This is where Altium Designer® truly shines; you won’t have to use separate design tools to create a schematic, capture it as a layout, route your signals, and perform important signal integrity simulations. Instead, everything you need runs on top of a rules-driven design engine, where layout and routing constraints are accessible across all your design tools.