How Vias Can Affect Very High-speed Signals

In a variety of articles posted on Altium’s resource center as well as in several other technical articles, papers, and conference proceedings, the advantages of differential signaling and its ability to deliver very high data rates have been touted. But, as with many things in life, those things that are beneficial can also have a downside. Such is the case with today’s products that deliver 32 Gbps and above data rates and the vias that are used to connect signal pins to the inner layers of a PCB. Where we were once able to ignore the effect of these vias at lower clock frequencies, with a product at higher data rates, via capacitance can be the source of signal degradation almost to the point of failure.

This article will describe these vias, how they affect short nets and how they can be best addressed from a design standpoint in those products operating at very high data rates.

The Definition of a Via and its Operational Characteristics

Vias are the holes drilled in or through a PCB that provides electrical access from one layer to another. For purposes of this discussion, a via refers to any plated through hole that is used to connect a signal trace to a component pin or a connector pin. The operational characteristics of this structure include:

• A via has distributed inductance along its length just like any other conductor.
• A via also has distributed capacitance along its length formed by the barrel of the plated hole and the surrounding planes through which it travels.
• When a signal travels the whole length of the via the two parasitics, capacitance and inductance, form a transmission line much like any signal trace.
• When the signal travels only part of the length of the via some of the capacitance is left hanging off the signal trace. This is often mistakenly identified as a “via stub”.

Figure 1 shows the effects of the previous operations. The layer changing via is located in the center of each trace.

Figure 1. Signals Traveling Various Lengths of a Layer-Changing Via

In the left-hand waveform, the signal is only traveling part way along the via. This creates a negative-going reflection which is to be expected when a small capacitor is attached to a signal trace. In most cases, this small reflection does no harm and these vias are freely used. (The negative-going reflection at the start of the waveform is the via used to access the trace with a TDR.) When the signal travels the full length of the via as shown in the right-hand waveform, this capacitance is spread along the length of the via, and the result is a very small reflection that is positive going. This indicates that there is a very small decrease in capacitance. This is due to the fact that the via used in this manner has an impedance slightly higher than the 50-ohm trace of which it is a portion. Essentially the via has been made to “disappear”.

Figure 2 shows the loss vs frequency for two different signal paths. The characteristics of these paths are:

• Both paths are 8” (20 cm) long.
• Each path has a 12-mil (.3 mm) drilled via at each end.
• The PCB is 108 mils (2.47 mm) thick.
• The red trace is the loss vs. frequency for the signal that was routed on Layer 14 of the 16-layer PCB.
  • This allowed the signal to travel nearly the full length of the via.
• The blue trace is the loss vs. frequency for the signal that is routed on Layer 3 of the same 16-layer PCB. As can be seen there is severe attenuation at 8 GHz on the blue waveform.
  • If this blue trace was the signal path for a PCIExpress Gen 4 signal, the link would likely fail due to excessive attenuation.

Figure 2. Loss vs. Frequency for Two Different Signal Paths

The equivalent circuit of the two signals measured in Figure 2 is shown in Figure 3. As the energy traveling down the transmission line encounters each via, a small amount of it reflects back toward the source. When the remaining energy encounters the second via, again, some reflects back and encounters the first via. If the frequency is just right this energy reflects back and forth, is trapped there, and becomes attenuated. An RF engineer might refer to this as a “low pass filter”.

Figure 3. Equivalent Circuit for the Signals in Figure 2

The shape of the loss curve resulting from multiple vias on a net is dependent on two things:

• The size of the vias.
• The length of the connecting trace.

For the vias used for press-fit connectors on backplanes, the via capacitance can be as large as 2 pF. This can result in attenuation at much lower frequencies than those depicted in Figure 2.

Why Long Nets Aren’t a Problem

Reference 1 at the end of this article describes a case where none of the long 10 Gb/S nets in a server design failed, but the short ones did. Most engineers focus on making sure that the loss in the long nets is low enough that they do not fail. They assume that the short nets will be fine. In the example contained in reference 1, the long and the short nets had the same number of vias. The long nets were all fine, but the short ones failed. The reason the long nets didn’t suffer from the problem shown in Figure 2 is that there was enough loss in the signal path that the reflections were attenuated and did not cause any problems. This is an example of how loss can be your friend.

Mitigating the Effects of Vias in Short Nets

Since the unwanted capacitance hanging off signal traces can cause unwanted resonances and excessive attenuation of a signal, it is desirable to minimize its presence. There are several ways to accomplish this. The types of vias and their merits and drawbacks are listed below.

• Use no vias; begin and end very high-speed signals on layer 1.
  • Merit:
    • This is a very good choice as long as there is room for all of the signals on Layer one.
  • Drawback:
    • This approach won’t work for a backplane. Also, because L1 is an outer layer, it is the poorest choice for impedance control.

• Travel the length of the vias by routing high-speed signals only on the lower layers.
  • Merit:
    • This is the best choice as long as there is room on the lower layers for all the signals. Besides, impedance control is very good, and there is no added cost. At Speeding Edge, we have designed several PCBs using this technique where there were dozens of 28 Gb/S differential pairs, and we had very good results.

• Route signals in any layer and back drill away the part of the via below the trace layer.
  • Merit:
    • This approach is necessary for backplanes as all signal layers are likely to be used for very fast signals.
  • Drawback:
    • Back drilling is a second operation after the PCB has gone through all of the fabrication steps and has a significant added cost. There is also the risk of drilling too deep and severing connections to trace layers.

• Route the signal on Layer 2 and provide access at both ends with a laser-drilled blind via.
  • Merit:
    • This method represents the best tradeoff between manufacturability and signal integrity as a blind via has virtually no added capacitance. Laser drilling blind vias are done at the same time as the through hole vias and only requires a very small processing change.
  • Drawback:
    • The disadvantage of this approach is that there may not be enough room on Layer 2 for all of the signals. Figure 4 is an example of routing a 10 Gb/S signal pair on Layer 2 with blind vias used for access.

Figure 4. A Laser-Drilled Blind Via Accessing a 10 Gb/S Differential Pair on Layer 2

Boomerang Vias

One of the Intel design guides for PCIExpress talks about using a “boomerang” via next to the edge connectors that plug into motherboards. This via is placed next to the via that is attached to the connector pin. When a high-speed signal is routed to the connector on Layer 1 it could suffer the same signal integrity problem described above if this via is hanging down from the trace. The signal is connected to the boomerang via and taken to the bottom of the PCB to eliminate the problem. On the bottom of the PCB, a trace is used to connect the boomerang via to the connector via causing the signal to travel the length of both vias.

Summary

As the speeds of differential pairs continue to increase, small discontinuities, such as vias, can cause catastrophic failures. Managing these discontinuities has become a critical part of the layout rule set for engineers and PCB designers. If these rules are carefully constructed, it is possible to achieve data rates as high as 56 Gb/S using high-performance laminates and standard PCB fabrication processes.

Have more questions? Call an expert at Altium.

References:

1. 7-TA3- Short May Not Be Better- Mike Steinberger, et al. DesignCon 2010.
2. Signal Integrity Verification of Via Stubs In DDR4 Memory, Benjamin Dannan 2020.