What Are PCB Vias and How They Affect High Speed Signals

In a variety of articles posted on Altium’s resource center as well as in several other technical articles, papers, and conference proceedings, the advantages of differential signaling and its ability to deliver very high data rates have been touted. But, as with many things in life, those things that are beneficial can also have a downside. Such is the case with today’s products that deliver 32 Gbps and above data rates and the vias that are used to connect signal pins to the inner layers of a PCB. Where we were once able to ignore the effect of these vias at lower clock frequencies, with a product at higher data rates, via capacitance can be the source of signal degradation almost to the point of failure.

This article will describe these vias, how they affect short nets and how they can be best addressed from a design standpoint in those products operating at very high data rates.

What is a PCB Via and Its Operational Characteristics

Vias are the holes drilled in or through a PCB that provide electrical access from one layer to another. For purposes of this discussion, a via refers to any plated through hole that is used to connect a signal trace to a component pin or a connector pin. The operational characteristics of this structure include:

• A via has distributed inductance along its length just like any other conductor.
• A via also has distributed capacitance along its length formed by the barrel of the plated hole and the surrounding planes through which it travels.
• When a signal travels the whole length of the via the two parasitics, capacitance and inductance, form a transmission line much like any signal trace.
• When the signal travels only part of the length of the via some of the capacitance is left hanging off the signal trace. This is often mistakenly identified as a “via stub”.

Figure 1 shows the effects of the previous operations. The layer changing via is located in the center of each trace.

Figure 1. Signals traveling various lengths of a layer-changing via

In the left-hand waveform, the signal is only traveling part way along the via. This creates a negative-going reflection which is to be expected when a small capacitor is attached to a signal trace. In most cases, this small reflection does no harm and these vias are freely used. (The negative-going reflection at the start of the waveform is the via used to access the trace with a TDR.) When the signal travels the full length of the via as shown in the right-hand waveform, this capacitance is spread along the length of the via, and the result is a very small reflection that is positive going. This indicates that there is a very small decrease in capacitance. This is due to the fact that the via used in this manner has an impedance slightly higher than the 50-ohm trace of which it is a portion. Essentially, the via has been made to “disappear”.

Figure 2 shows the loss vs frequency for two different signal paths. The characteristics of these paths are:

• Both paths are 8” (20 cm) long.
• Each path has a 12-mil (.3 mm) drilled via at each end.
• The PCB is 108 mils (2.47 mm) thick.
• The red trace is the loss vs. frequency for the signal that was routed on Layer 14 of the 16-layer PCB.
  • This allowed the signal to travel nearly the full length of the via.
• The blue trace is the loss vs. frequency for the signal that is routed on Layer 3 of the same 16-layer PCB. As can be seen there is severe attenuation at 8 GHz on the blue waveform.
  • If this blue trace was the signal path for a PCIExpress Gen 4 signal, the link would likely fail due to excessive attenuation.

Figure 2. Loss vs. frequency for two different signal paths (includes via and transmission line sections)

The equivalent circuit of the two signals measured in Figure 2 is shown in Figure 3. As the energy traveling down the transmission line encounters each via, a small amount of it reflects back toward the source. When the remaining energy encounters the second via, again, some reflects back and encounters the first via. If the frequency is just right this energy reflects back and forth, is trapped there, and becomes attenuated. An RF engineer might refer to this as a “low pass filter”.

Figure 3. Equivalent circuit for the signals in Figure 2. This equivalent circuit lumps the transmission line sections, via, and antipad in the plane layers into a single circuit.

The shape of the loss curve resulting from multiple vias on a net is dependent on two things:

• The dimensions of the vias.
• The length of the connecting trace.
• The presence of nearby stitching vias (primarily on single-ended via transitions).

For the vias used for press-fit connectors on backplanes, the via capacitance can be as large as 2 pF. This can result in attenuation at much lower frequencies than those depicted in Figure 2.

Equivalent T-Line + Via Circuit vs. Vias Alone

The equivalent circuit above is not exactly complete... it is intended to show the ideal case where via antipad to nearby planes creates a small impact on the performance of the channel. In reality, there is via inductance, but the inductance could be minimized with the right geometry. At very high frequencies near the via's bandwidth limit, a via that is matched to the target impedance can still experience loss at high frequencies; this is most easily modeled from the circuit perspective as a shunt capacitor, as shown above, as it accounts for the rollover in the insertion loss curve. Yuriy Shlepnev refers to this as "localization" where, above some frequency, the via starts to look lossy because electromagnetic energy is able to escape the region around the vias.

Vias themselves can have very strange impedance curves, where the via initially looks inductive above a few GHz, but then looks capacitive at much higher frequencies. An example prepared from Simbeor is shown below.

So clearly, the vias on their own can have very bad impedance curves. This can explain why sometimes a very short connection through a via can have much worse performance than a very long connection through the same via. The conventional design wisdom would state that the (T-lines + vias) circuit should be optimized for minimum insertion loss due to its length, therefore a shorter total route length would perform even better due to lower total insertion loss. This is actually not always the case, because in a short connection through a via going directly to a load, the via and load impedance create a significant difference in the input impedance, leading to high return loss.

Although an individual via might have very bad impedance matching in different frequency ranges, what matters is how the signal travels into and out of the via on the connected transmission lines. This is determined by the input impedance looking through the via, and it should explain why a bad via can still work acceptably in different frequency ranges. If the input impedance through the via is not too much deviated from the target impedance in the required frequency range, then the via is still acceptable.

Note that this does not include other important effects, such as stubs on through-hole vias. The points discussed here will apply to single-ended vias and differential vias.

Stitching Vias: Do They Matter?

The short answer is yes, but only above a certain frequency range, and the degree to which they matter depends on whether you are routing single-ended channels or differential pairs.

Below about 3 GHz, a via transition is electrically short, and its input impedance will look close enough to the trace impedance that a single nearby ground return via is sufficient. Above 3 to 5 GHz, the situation changes. A via transition without stitching vias will present an inductive impedance that rises with frequency, reaching roughly 3 to 4 times the via's characteristic impedance by about 30 GHz. Above 30 GHz, parasitic capacitance begins to dominate and the impedance drops back down, but the damage in the midrange frequencies is already done: you lose power in the form of return loss at the via transition, and insertion loss through the channel degrades in exactly the bandwidth where your signal energy needs to pass cleanly. For channels operating at 56 Gbps NRZ or 112G PAM-4 rates, this impedance deviation across the 5 to 50 GHz range is where via transitions either work or fail.

Stitching vias placed around a signal via, combined with antipad sizing, determine the parallel capacitance seen by the signal via as it passes through plane layers. Moving the stitching vias and antipad boundary closer to the signal via increases this capacitance, which pulls the via's characteristic impedance down toward the target. The goal is to flatten the input impedance across the full signal bandwidth so that the transition does not behave like a lumped reactive discontinuity.

For differential pairs, the antipad geometry dominates the impedance tuning. The differential mode fields are concentrated between the two signal vias, and the antipad boundary in the reference planes sets the capacitive loading on that mode. For single-ended channels, the sensitivity is more evenly distributed between antipad size and stitching via placement. Getting the stitching via count and spacing wrong on a single-ended transition has a more immediate effect on impedance than it does for a differential pair.

There is a real risk of over-correction. If the stitching vias and antipad boundary are brought too close, the added capacitance will pull the input impedance below the target in the 5 to 50 GHz range. The result is a capacitive dip rather than an inductive rise, and the return loss penalty is comparable. Achieving flat impedance across a wide bandwidth requires electromagnetic field simulation using tools like CST or Simbeor. Every via impedance calculator based on closed-form analytical models produces incorrect results in the frequency ranges where via impedance actually matters, because the cylindrical geometry of via arrays involves Bessel and Neumann function relationships that have no tractable closed-form solution for real PCB structures.

Mitigating Via Effects in Short Nets

Since the unwanted capacitance hanging off signal traces can cause unwanted resonances and excessive attenuation of a signal, it is desirable to minimize its presence. There are several ways to accomplish this. The types of vias and their merits and drawbacks are listed below.

• Use no vias; begin and end very high-speed signals on layer 1.
  • Merit:
    • This is a very good choice as long as there is room for all of the signals on Layer one.
  • Drawback:
    • This approach won’t work for a backplane. Also, because L1 is an outer layer, it is the poorest choice for impedance control.
       
• Travel the length of the vias by routing high-speed signals only on the lower layers.
  • Merit:
    • This is the best choice as long as there is room on the lower layers for all the signals. Besides, impedance control is very good, and there is no added cost. At Speeding Edge, we have designed several PCBs using this technique where there were dozens of 28 Gb/S differential pairs, and we had very good results.
       
• Route signals in any layer and back drill away the part of the via below the trace layer.
  • Merit:
    • This approach is necessary for backplanes as all signal layers are likely to be used for very fast signals.
  • Drawback:
    • Back drilling is a second operation after the PCB has gone through all of the fabrication steps and has a significant added cost. There is also the risk of drilling too deep and severing connections to trace layers.
       
• Route the signal on Layer 2 and provide access at both ends with a laser-drilled blind via.
  • Merit:
    • This method represents the best tradeoff between manufacturability and signal integrity as a blind via has virtually no added capacitance. Laser drilling blind vias are done at the same time as the through hole vias and only requires a very small processing change.
  • Drawback:
    • The disadvantage of this approach is that there may not be enough room on Layer 2 for all of the signals. Figure 4 is an example of routing a 10 Gb/S signal pair on Layer 2 with blind vias used for access.

Figure 4. A laser-drilled blind via accessing a 10 Gbps differential pair on layer 2

Boomerang Vias

One of the Intel design guides for PCIExpress talks about using a “boomerang” via next to the edge connectors that plug into motherboards. This via is placed next to the via that is attached to the connector pin. When a high-speed signal is routed to the connector on Layer 1 it could suffer the same signal integrity problem described above if this via is hanging down from the trace. The signal is connected to the boomerang via and taken to the bottom of the PCB to eliminate the problem. On the bottom of the PCB, a trace is used to connect the boomerang via to the connector via causing the signal to travel the length of both vias.

Summary

As the speeds of differential pairs continue to increase, small discontinuities, such as vias, can cause catastrophic failures. Managing these discontinuities has become a critical part of the layout rule set for engineers and PCB designers. If these rules are carefully constructed, it is possible to achieve data rates as high as 56 Gb/S using high-performance laminates and standard PCB fabrication processes.

Designing high‑speed differential pairs is no longer just about getting the physics right. As data rates rise, the risk increasingly comes from workflow breakdowns around the design: unclear versions, disconnected reviews, late sourcing questions, and manual release prep that leaves room for avoidable surprises. 

Altium Develop is built for this stage of the work. It provides a clearer path from active layout decisions, like via strategy, layer transitions, and back‑drilling choices, to review, handoff, and release readiness. Get started with Altium Develop today →